Machine Learning (ML) has shown promising results in predicting the behavior of analog circuits. However, in order to completely cover the design space for today's complicated circuits, supervised ML ...requires a large number of labeled samples which is time-consuming to provide. Furthermore, a separate dataset must be collected for each circuit topology making all other previously gathered datasets useless. In this paper, we first present a database including labeled and unlabeled data. We use neural networks to determine the behavior of complicated topologies by combining the more simple ones. By generating such unlabeled data, the time for providing the training set is significantly reduced compared to the conventional approaches. Using this database, we propose a fully-automated analog circuit generator framework, AnGeL. AnGeL performs all the schematic circuit design steps from deciding the circuit topology to determining the circuit parameters i.e. sizing. Our results show that for multiple circuit topologies, in comparison to the state-of-the-art works while maintaining the same accuracy, the required labeled data is reduced by 4.7x -1090x. Also, the runtime of AnGeL is 2.9x -75x faster.
A new common-mode bandstop filter (CM-BSF) with an all-pass performance (from dc to 9 GHz) for differential signals is proposed by using a C-shaped patterned ground structure (PGS) with meandered ...signal lines on a two-layer printed circuit board (PCB). This technique can successfully generate two close transmission zeros in common-mode within the frequencies of concern. A corresponding equivalent circuit model is established to predict the filter behaviors, and a formula for common-mode transmission zeros is derived based on the circuit model. Next, a design method is developed and a synthesis procedure is proposed. According to the procedure, a wideband CM-BSF is synthesized and fabricated on a two-layer PCB. In addition, the simulation and experiment results are demonstrated to verify the technique and show excellent performance of the proposed CM-BSF. It is shown that common-mode noise can be suppressed over 10 dB from 1.9 to 8.9 GHz with 130% fractional bandwidth (FBW) while the insertion loss of differential-mode can be kept less than 3 dB from dc to 9 GHz. The electrical size is only 0.21 λ g ×0.21 λ g , where λ g is the wavelength of the stopband central frequency. To sum up, the proposed CM-BSF has merits of low cost (two layer), a simple geometric structure, a compact size, and a large common-mode FBW. Most importantly, the filter can keep good signal integrity of the digital differential signals due to its all-pass characteristic.
We propose a logic synthesis methodology with a novel low-power circuit structure for ternary logic. The proposed methodology synthesizes a ternary function as a ternary logic gate using carbon ...nanotube field-effect transistors (CNTFETs). The circuit structure uses the body effect to mitigate the excessive power consumption for the third logic value. Energy-efficient ternary logic circuits are designed with a combination of synthesized low-power ternary logic gates. The proposed methodology is applicable to both unbalanced (0, 1, 2) and balanced (−1, 0, 1) ternary logic. To verify the improvement in energy efficiency, we have designed various ternary arithmetic logic circuits using the proposed methodology. The proposed ternary full adder has a significant improvement in the power-delay product (PDP) over previous designs. Ternary benchmark circuits have been designed to show that complex ternary functions can be designed to more efficient circuits with the proposed methodology.
A nanoprocessor constructed from intrinsically nanometre-scale building blocks is an essential component for controlling memory, nanosensors and other functions proposed for nanosystems assembled ...from the bottom up. Important steps towards this goal over the past fifteen years include the realization of simple logic gates with individually assembled semiconductor nanowires and carbon nanotubes, but with only 16 devices or fewer and a single function for each circuit. Recently, logic circuits also have been demonstrated that use two or three elements of a one-dimensional memristor array, although such passive devices without gain are difficult to cascade. These circuits fall short of the requirements for a scalable, multifunctional nanoprocessor owing to challenges in materials, assembly and architecture on the nanoscale. Here we describe the design, fabrication and use of programmable and scalable logic tiles for nanoprocessors that surmount these hurdles. The tiles were built from programmable, non-volatile nanowire transistor arrays. Ge/Si core/shell nanowires coupled to designed dielectric shells yielded single-nanowire, non-volatile field-effect transistors (FETs) with uniform, programmable threshold voltages and the capability to drive cascaded elements. We developed an architecture to integrate the programmable nanowire FETs and define a logic tile consisting of two interconnected arrays with 496 functional configurable FET nodes in an area of ∼960 μm(2). The logic tile was programmed and operated first as a full adder with a maximal voltage gain of ten and input-output voltage matching. Then we showed that the same logic tile can be reprogrammed and used to demonstrate full-subtractor, multiplexer, demultiplexer and clocked D-latch functions. These results represent a significant advance in the complexity and functionality of nanoelectronic circuits built from the bottom up with a tiled architecture that could be cascaded to realize fully integrated nanoprocessors with computing, memory and addressing capabilities.
Test structures utilizing ring oscillators to monitor MOSFET ac characteristics for digital CMOS circuit applications are described. The measurements provide information on the average behavior of ...sets of a few hundred MOSFETs under high speed switching conditions. The design of the ring oscillators is specifically tailored for process centering and monitoring of variability in circuit performance in the manufacturing line as well as in the product. The delay sensitivity to key MOSFET parameter variations in a variety of ring oscillator designs is studied using a compact model for partially depleted silicon on insulator(PD-SOI) technology, but the analysis is equally valid for conventional bulk Si technology. Examples of hardware data illustrating the use of this methodology are taken primarily from experimental hardware in the 90-nm CMOS technology node in PD-SOI. The design and data analysis techniques described here allow very rapid investigation of the sources of variations in circuit delays.
Machine learning-assisted global optimization methods for speeding up analog integrated circuit sizing is attracting much attention. However, often a few typical analog integrated circuit design ...specifications are considered in most relevant research. When considering the complete set of specifications, two main challenges are yet to be addressed: 1) the prediction error for some performances may be large and the prediction error is accumulated by many performances. This may mislead the optimization and fail the sizing, especially when the specifications are stringent and 2) the machine learning cost could be high considering the number of specifications, considerably canceling out the time saved. A new method, called efficient surrogate model-assisted sizing method for high-performance analog building blocks (ESSAB), is proposed in this article to address the above challenges. The key innovations include a new candidate design ranking method and a new artificial neural network model construction method for analog circuit performance. Experiments using two amplifiers and a comparator with a complete set of stringent design specifications show the advantages of ESSAB.
An experimental analysis of the behavior under short-circuit conditions of three different silicon-carbide (SiC) 1200-V power devices is presented. It is found that all devices take up a substantial ...voltage, which is favorable for detection of short circuits. A transient thermal device simulation was performed to determine the temperature stress on the die during a short-circuit event, for the SiC MOSFET. It was found that, for reliability reasons, the short-circuit time should be limited to values well below Si IGBT tolerances. Guidelines toward a rugged design for short-circuit protection (SCP) are presented with an emphasis on improving the reliability and availability of the overall system. A SiC device driver with an integrated SCP is presented for each device-type, respectively, where a short-circuit detection is added to a conventional driver design in a simple way. The SCP driver was experimentally evaluated with a detection time of 180 ns. For all devices, short-circuit times well below 1 μs were achieved.
Improving the on-current has been the focus of enhancing the performance of tunnel field-effect transistors (TFETs). In this paper, we show that the increase in I_ON is not sufficient to improve the ...circuit performance with TFETs. As TFETs show a drain-barrier voltage in their output characteristics below which the drain current drastically reduces, the rise/fall time significantly increases. This reduces the dynamic noise margin and limits the performance achievable from TFETs. We show that, in TFETs, the delay of the circuit is determined by the rise/fall time rather than by the propagation delay. The saturation voltage is much higher compared with that of complementary metal-oxide-semiconductor (CMOS) devices, leading to a lower gain and a lower static noise margin in digital circuits, as well as impeding the performance of latch/regenerative circuits. We present a design space comprising of I_ON, a drain saturation voltage, and a drain threshold voltage for minimizing the propagation delay of circuits using TFETs. Finally, for the same off-current and speed of operation, TFET devices tend to suffer from a higher gate capacitance compared with CMOS devices. If this behavior is not taken into account during the circuit design, these devices (although designed for low-power applications) can dissipate more power at the same speed of operation than CMOS counterparts.
Dual Chua's Circuit Wang, Ning; Xu, Dan; Iu, Herbert Ho-Ching ...
IEEE transactions on circuits and systems. I, Regular papers,
03/2024, Volume:
71, Issue:
3
Journal Article
Peer reviewed
As a classic paradigm of chaos generation, Chua's circuit has been widely studied and applied in different fields. Various Chua's circuits employing voltage-controlled Chua's diodes have been ...designed and implemented, but rare such circuits employing current-controlled Chua's diodes have been reported to date. Following the technical steps which Chua used to design the famous Chua's circuit, this paper presents a systematic design procedure of the chaotic circuits employing current-controlled nonlinear resistors. Two simple circuit topologies are presented as paradigms, which respectively are dual to the classical Chua's circuit and the canonical Chua's circuit. In specific, we obtain two simple implementations of the dual Chua's circuits consisting of two inductors, one capacitor, one passive/active linear resistor, and one piecewise-linear current-controlled Chua's diode. The numerical simulations and the previously unreported physical implementations confirmed the feasibility of the design. Consequently, it enriches the genealogy of the Chua's circuit family.
A novel method for designing and realising compact digital circuits by engineering MOSFET gate electrode is proposed. The novelty is the use of gate engineered single devices in the pull-up (PU) and ...pull-down (PD) paths of a static CMOS gate instead of multiple transistors as used in conventional CMOS implementations of circuits. Herein, two input NAND, NOR, and exclusive-OR (XOR) gates employing the proposed gate engineering concept are designed and simulated. Engineered gate N-type MOS and P-type MOS are used for PD and pull-up circuits, respectively. Since only two devices are used for a complete circuit: one in PU network and other in PD network; therefore, area and power of the proposed circuits get reduced significantly in comparison with the conventional static CMOS circuits. Mixed mode simulations have shown that the proposed technique realises NAND, NOR and XOR operations perfectly and it can be extended to realise other combinational and sequential circuits easily.
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