•Effects of Ag sintering parameters on shear strength of die attachment are revealed.•Modes of shear failure depending on bonding strength of sintered Ag are observed.•Linear relationships between ...shear strength, porosity and thicknesses are explored.
3mm×3mm dummy SiC dies with 100\200\200nm thick Ti\W\Au metallization have simultaneously been attached using sintering of Ag nanoparticle paste on AlN-based direct bonded copper substrates with 5\0.1μm thick NiP\Au finish. The effect of preparation and sintering parameters including time of drying the printed paste, sintering temperature and time, and pressure, on the average shear strength for multiple die attachments was investigated. The surfaces of the die attachments after the shear tests were observed and the individual shear strength values correlated with the “apparent” porosity and thicknesses of the corresponding die attachments (sintered layer). The results obtained are further discussed and compared with typical data reported in existing literature. Main conclusions include: (i) the present shear strength values and their variations are comparable with those reported for single die attachment samples, (ii) the effects of sintering parameters can be ascribed to the effectiveness of the organic content burnout and appropriate rate of growth and coalescence of the Ag nanoparticles during the sintering process, and (iii) thickness values of the sintered Ag die attachments may be taken as non-destructive measurements to monitor/evaluate the quality of die attachment during power electronic module manufacturing/assembly process.
The purpose of this paper is to present analyses of the junction temperature of planar power 4H-SiC MOSFET under short-circuit events especially when failure appears. To characterize the junction ...temperature related to this failure type, various planar power SiC MOSFETs from several manufacturers were studied. The junction temperature during a short circuit was estimated using ANSYS Multiphysics software with dimensions and physical parameters of each device individually adjusted according to its experimental characteristics. Obtained results approximatively show the same junction temperature rating at instant of failure overall devices under test. This junction temperature threshold seems to be responsible for thermal runaway phenomenon triggering the failure process. Below this critical junction temperature, the device can safely turn-off the short circuit current or fail into a “soft failure” due to a short circuit between gate and source.
•The junction temperature of planar power 4H-SiC MOSFET under short-circuit events has been investigated.•A junction temperature threshold seems to be responsible for thermal runaway phenomenon triggering the failure process.•Below the critical junction temperature, the device can safely turn-off the SC current or fail into a “soft failure”.
In power circuits, the gate drivers are required to provide an optimal and safe switching of power semiconductor devices. Nowadays, the gate driver boards include more and more features, such as ...short-circuit detection, soft-shutdown, temperature sensing, on -state voltage monitoring. Research works are in progress on the integration of on-line monitoring features for a predictive maintenance. The instrumentation of the gate drive system supposes the integration of a communication system to transmit the monitoring data. In high-power designs, a galvanic isolation is mandatory on the gate driver board. The parasitic capacitance seen on the isolation barrier is critical in these designs as it can lead to the circulation of common mode currents during the switching. Adding extra optocouplers or transformers on the isolation barrier is, therefore, risky due to electromagnetic interference constraints. In this article, a new bidirectional data transmission method is proposed for gate drivers used for driving 1.2 kV silicon carbide (SiC) power metal oxide semiconductor field effect transistors ( mosfet s). The proposed method enables the energy transmission and a bidirectional data exchange on a single power supply transformer. The experimental results are provided demonstrating 1 Mb/s for TxD and 16 kb/s for RxD. The targeted application is the health monitoring of SiC power mosfet s using the gate driver board.
The use of local and rapid heating of electronic assemblies can significantly reduce the degradation of temperature-sensitive materials and substrate bowing commonly encountered in electronic ...applications during the high temperature reflow process. It can also allow assembling electronic packages on a non-planar surface and/or on massive structures that are very complex using a conventional oven for soldering. In order to attach electronic components to substrates, a rapid soldering process using an exothermic reactive foil sandwiched between solder preforms was evaluated. Once the film was activated and reacted, the solder preforms were melted to ensure the adhesion between the assembled materials. The effect of applied pressure on the joint quality, the reactive film thickness, as well as the attached material thickness and physical properties were assessed. Using a 60 μm thick reactive foil with two 25 μm thick SnAgCu305 preforms, results show that the fraction of void-free interfacial area between a metallized diode and an active metal braze substrate increased from 34% to 74% with pressure values between 0.5 kPa and 100 kPa, respectively. At a constant pressure of 13 kPa, increasing the reactive foil thickness from 40 μm to 60 μm leads to an increase in the void-free interfacial attach area ratio from 20% to 40%, and a value of 54% was achieved by using two 60 μm foils under the same conditions. The substrate metallization and solder thickness also affect the joint quality. The experimental results are analyzed and correlated with the duration of liquid solder using thermal models.
Silicon Carbide (SiC) power transistors are more and more used in electric energy conversion systems. SiC power semiconductors devices, such as SiC metal-oxide-semiconductor field-effect transistor ( ...mosfet ) can operate at higher frequency and higher temperature compared to Silicon power mosfet or insulated-gate bipolar transistor. However, the maturity of the SiC technology is moderate compared to the well-known Silicon-based power semiconductor devices. Recent research works on reliability of SiC power mosfet identified gate leakage currents as an ageing indicator. The monitoring of ageing indicators during normal operation may definitely help to predict damages and simplify the maintenance on the energy conversion systems. Due to the low amplitude of gate leakage currents, its direct measurement is difficult even under laboratory conditions and requires an offline characterization. This article presents a new method for estimating the gate leakage current using the gate drive circuit. The proposed method takes advantage of the internal structure of the typical gate drivers used to command SiC power mosfet s.
The proposed dual-port gate driver architecture relies on a quasi-flying gate concept to protect SiC power MOSFETs against short-circuit events. Hard Switching Faults (HSF) extract charges from the ...gate by causing a leakage current towards the source, while Faults Under Load (FUL) lead to charge injection into the gate through the reverse transfer capacitance (C GD ). Such phenomena lead to perturbations of the gate-source voltage (V GS ) which are amplified by the gate resistor, acting as an enhancer of short-circuit signatures. Thus, a small gate resistance is used to ensure high switching dynamics, while a larger one is switched on during PWM on-state operation to identify possible faults. A dual-port gate driver is then proposed to ensure fast switching with HSF and FUL monitoring. The fault detection scheme relies on comparing two thresholds to V GS relative changes to the nominal gate voltage. Experimental results using TO-247 package 1.2 kV/36 A SiC MOSFETs exhibit promising inverter leg short-circuit detection and protection against faults in less than 300 ns.
In this paper, we study the effect of aging of SIC MOSFETs on Short Circuit Safe Operating Area and Reverse Bias Safe Operating Area of SiC MOSFETs. SCSOA and RBSOA are determined using short circuit ...and unclamped inductive switching tests, respectively. Aging of SiC MOSFETs are performed with repetitive short circuit tests at low dissipated energies, which allows to validate the relevance of evolution of different aging indicators measured during the aging process. The decrease in the dissipated energy leading to failure in short circuit and unclamped inductive switching tests allows to clearly link the evolution of these Safe Operating Areas to the degradation of electrical performances (drain and gate leakage currents and on-state resistance). Obtained results show that a strong increase in the drain and/or gate leakage currents after aging has a great effect on the decrease of Safe Operating Area especially on RBSOA and that on-state resistance increase due to aging process represents less impacts in the evolution of RBSOA than in the case of SCSOA. It is also clear from the obtained results that without any apparent evolution of these leakage currents, the decrease of SCSOA after aging is related to the increase in the on-state resistance.
•The effect of short circuit aging on SCSOA and RBSOA of SiC MOSFETs has been investigated.•The obtained results allow to point out different pertinent aging indicators.•The evolution of SCSOA and RBSOA was linked to the degradation of electrical performances of SiC MOSFET.
This paper presents short-circuit (SC) performance of a commercial silicon-carbide (SiC) MOSFET device under repetitive SC stress at high drain source voltage. Two protocols are investigated to ...evaluate the impact of gate-source voltage (VGS) depolarization and SC duration (TSC) reduction. The VGS depolarisation provides a power density reduction and allows to preserve a secure failure mode (FTO: Fail To Open) with an increase of the short circuit duration TSCmax. The results demonstrate that SiC MOSFET VGS depolarization does not reduce SC cycling capability at TSCmax. However, using VGS depolarization allows to get performance close to IGBT robustness levels with almost 1000 cycles @TSC = 10 μs. The simulation of the chip temperature evolution during SC tests suggests that the degradations stay attributed to the increase of junction temperature (TJ) during the SC cycles, which leads to the fusion of the top Al inducing cracks into the thick oxide.
This paper focuses on the enhancement of the robustness level of SiC MOSFET during short-circuit conditions. In this study, two approaches allowing to ensure safe “Fail-To-Open” (FTO) mode in planar ...power SiC MOSFET devices under short-circuit operation are presented. These approaches are based on direct depolarization of the gate source voltage and its estimation from the calculation of the critical dissipated power (W/mm2) between FTO and classical unsafe thermal runaway. They allow to determine the maximum value of the gate source voltage to preserve a FTO mode under a drain source voltage close to the nominal value i.e. VBRmin/2. The boundary of the power density between FTO and “Fail-To-Short” (FTS) is introduced. A complete experimentation of the two failure modes in competition that may appear during short-circuit (SC) test of 1.2 kV SiC MOSFETs is presented. Finally, the penalty of the gate source voltage depolarization on the on-state resistance (Rds(on)) is investigated in order to evaluate the techniques efficiency.
•We compare 3 die-attach technologies for high temperature power electronics packaging.•Micro and nano silver sintering processes and AuGe solder alloy process are presented.•After high thermal ...ageing test, the results showed very high die shear strenght capability.•No evolution of the AuGe solder alloy joint is observed after 2500 thermal shocks cycles.•High range of temperature was used for the ageing test (-55°C to +245°C).
Silver sintering joints and AuGe soldering are promising technologies for high temperature (>200°C ambient) power electronics packaging. This paper presents the implementation of two silver-sintering processes with the one hand micrometer-scale silver particles, and on the other hand nano-meter-scale particles. Two substrates technologies have been investigated: A12O3 DBC and Si3N4 AMB. After the process optimization, tests vehicles have been assembled using both sintering processes, as well as a more classical high-temperature die attach technology: AuGe soldering. Multiple analyses have been performed, such as thermal resistance measurement, shear tests and micro-sections to follow the evolution of the joint during thermal cycling and high-temperature storage ageing.
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