As CMOS technology scales down, digital supply voltage and digital power consumption goes down. However, the supply voltage and power consumption of the RF front-end and analog sections do not scale ...in a similar fashion. In fact, in many state-of-the-art communication transceivers, RF and analog sections can consume more energy compared to the digital part. In this paper, first, a system level energy model for all the components in the RF and analog front-end is presented. Next, the RF and analog front-end energy consumption and communication quality of three representative systems are analyzed: a single user point-to-point wireless data communication system, a multi-user code division multiple access (CDMA)-based system and a receive-only video distribution system. For the single user system, the effect of occupied signal bandwidth, peak-to-average ratio (PAR), symbol rate, constellation size, and pulse-shaping filter roll-off factor is analyzed; for the CDMA-based multi-user system, the effect of the number of users in the cell and multiple access interference (MAI) along with the PAR and filter roll-off factor is studied; for the receive-only system, the effect of 1/f noise for direct-conversion receiver and the effect of IF frequency for low-IF architecture on the RF front-end power consumption is analyzed. For a given communication quality specification, it is shown that the energy consumption of a wireless communication front-end can be scaled down by adjusting parameters such as the pulse shaping filter roll-off factor, constellation size, symbol rate, number of users in the cell, and signal center frequency
Current feedback amplifiers (CFAs) provide fast response and high slew rate with Class-AB operation. Fast response, low-dropout regulators (LDRs) are critical for supply regulation of deep-submicron ...analog baseband and RF system-on-chip designs. An LDR with an CFA-based second stage driving the regulation field-effect transistor is presented. The low dropout (LDO) achieves an output noise spectral density of 67.7 nV radicHz, and PSR of 38 dB, both at 100 kHz. In comparison to an equivalent power consumption voltage feedback buffer LDO, the proposed CFA-based LDO settles 60% faster, achieving 0.6- settling time for a 25-mA load step. The LDO with CFA buffer is designed and fabricated on a 0.25- CMOS process with five layers of metal, occupying 0.23- silicon area.
A combined class-AB and switch-mode regulator based supply modulator with a master-slave architecture achieving wide bandwidth and low ripple is presented. Low frequency content of the envelope ...waveform is provided by a synchronous-rectifier based switch-mode power supply while high frequency content is provided by a rail-to-rail class-AB amplifier. A wide range, low loss output current sensing circuit is used at the class-AB amplifier output, canceling the ripple due to switch-mode power supply and extending overall modulator bandwidth. The proposed regulator is designed and fabricated on a 0.35 mum CMOS process. The combined regulator achieves a maximum efficiency of 82% and an IMD3 of 65 dBc at 10 MHz for 16 dBm output power. The regulator achieves a frequency range up to 10 MHz with less than 0.2% envelope tracking error, making this PA regulator suitable for CDMA applications.
An on-chip clock phase-noise measurement circuit is presented. Unlike previously reported monolithic measurement techniques that measure jitter in the time domain, the proposed module measures the ...phase-noise spectrum. The proposed circuit is fully integrated and does not require a spectrally clean reference clock or any external calibration. The module can be integrated as part of a built-in self-test (BIST) scheme for PLL clock synthesizers. The proposed circuit uses a low-noise voltage-controlled delay-line (VCDL) and mixer-based frequency discriminator to extract the phase-noise fluctuations at baseband. A self-calibration circuit is used to operate the measurement circuit at its highest sensitivity point. The proposed circuit is fabricated using a 0.25 mum digital CMOS process and operates up to a 2 GHz carrier frequency. It achieves a single-tone measurement sensitivity of -75 dBc and an equivalent phase-noise sensitivity of -124 dBc/Hz at 100 kHz offset frequency.
A combined linear and delta-modulated (DeltaM) switch-mode PA supply modulator for polar transmitters in wireless handsets is designed in a 0.25 mum CMOS process. The modulator employs a DeltaM ...switch-mode DC-DC buck converter to enhance the efficiency of a linear regulator at backed-off supply voltages and powers. The delta-modulator's noise-shaping characteristic, linear regulator's power supply rejection, digital pre-emphasis of the input envelope, and a closed-loop amplitude path from the PA output are simultaneously used to achieve state-of-the-art modulator performance. The presented supply modulator follows the input signal's envelope with 20 dB output dynamic range, maximum efficiency of 75.5% at an output power of 30.8 dBm, and 75 dB SFDR for envelope signals up to 4 MHz occupied RF bandwidth. For a 1625 kb/s 8 PSK RF input signal at 900 MHz, polar modulation of a commercial low-power GSM-900 PA provides 10 dB ACPR improvement.
Two integrated polar supply-modulated class E and F power amplifiers (PAs) in 0.18-mum SiGe BiCMOS process are presented. The amplifiers are used to transmit GSM-EDGE signals with an envelope dynamic ...range of 11 dB and a frequency range of 880-915 MHz. The amplifiers use switch-mode dc-dc buck converters for supply modulation, where sigma-delta (SigmaDeltaM), delta (DeltaM), and pulsewidth modulation are used to modulate the PA amplitude signal. A framework has been developed for comparing the three switching techniques for EDGE implementation. The measurement results show that DeltaM gives the highest efficiency and lowest adjacent channel power, providing class E and F PA efficiencies of 33% and 31%, respectively, at maximum EDGE output power. The corresponding class E and F linearized amplifiers' output spectra at 400-kHz offset are -54 and -57dBc, respectively
An adaptive blocker-rejection wideband continuous-time (CT) sigma-delta (SigmaDelta) analog-to-digital converter (ADC) is presented. An integrated blocker detector reconfigures the ADC loop ...architecture to avoid overloading in the presence of strong interferers, improving receiver channel selectivity and sensitivity without increasing its dynamic range (DR) requirements. The adaptive operation relaxes receiver baseband channel filtering requirements for a worldwide inter-operability for microwave access (WiMAX, IEEE 802.16e) receiver. The ADC achieves 71 dB of dynamic range (DR), 65 dB of peak SNDR and 68 dB of peak SNR over a 10 MHz signal bandwidth, consuming 18 mW from a 1.2 V supply. The ADC system reconfigures the loop filter topology within 51 mus, improving receiver selectivity without any transient impact on BER. In the blocker suppression mode, the ADC can withstand 30 dBc blocker at the adjacent channel, achieving - 22 dB error vector magnitude (EVM) with a 24 Mb/s 16-QAM signal. The IC is fabricated on a 130 nm 8-level metal, metal-insulator-metal (MIM) capacitor, CMOS technology, occupying 1.5 times 0.9 mm 2 silicon area.
Systematic design of low-dropout-regulator (LDO) regulated low-phase-noise LC-tank voltage controlled oscillators (VCOs) is presented. Low-frequency sensitivity profile of power supply induced phase ...noise of a typical cross-coupled LC-tank VCO is investigated. The relationship between frequency pushing and power supply-induced phase noise is derived. Systematic codesign of VCO sensitivity to low-frequency supply noise with respect to an LDO output noise and power supply rejection profile is introduced. To demonstrate the design approach experimentally, two 2.4-GHz LC-tank VCOs with pMOS and nMOS switching devices powered by PFET LDOs are designed and fabricated on an 0.18-mum, 7-layer metal CMOS process. By using an integrated LDO, it is shown that the VCO phase-noise sensitivity to low frequency improves by 55 dB at 100-kHz offset.
Low 1/ f noise, low-dropout (LDO) regulators are becoming critical for the supply regulation of deep-submicron analog baseband and RF system-on-chip designs. A low-noise, high accuracy LDO regulator ...(LN-LDO) utilizing a chopper stabilized error amplifier is presented. In order to achieve fast response during load transients, a current-mode feedback amplifier (CFA) is designed as a second stage driving the regulation FET. In order to reduce clock feed-through and 1/ f noise accumulation at the chopping frequency, a first-order digital SigmaDelta noise-shaper is used for chopping clock spectral spreading. With up to 1 MHz noise-shaped modulation clock, the LN-LDO achieves a noise spectral density of 32 nV/radic(Hz) and a PSR of 38 dB at 100 kHz. The proposed LDO is shown to reduce the phase noise of an integrated 32 MHz temperature compensated crystal oscillator (TCXO) at 10 kHz offset by 15 dB. Due to reduced 1/ f noise requirements, the error amplifier silicon area is reduced by 75%, and the overall regulator area is reduced by 50% with respect to an equivalent noise static regulator. The current-mode feedback second stage buffer reduces regulator settling time by 60% in comparison to an equivalent power consumption voltage mode buffer, achieving 0.6 mus settling time for a 25-mA load step. The LN-LDO is designed and fabricated on a 0.25 mum CMOS process with five layers of metal, occupying 0.88 mm 2 .
An all-digital sliding-mode (ADSM) controlled dc-dc converter, utilizing single-bit oversampled frequency domain digitizers in its feedback path is proposed. Sliding-mode control provides several ...benefits over the traditional PID control in terms of fast transient response, robustness to parameter and component variations, and low sensitivity to loop disturbances. However, analog implementations of sliding-mode control require several amplifiers in the controller and suffer from process, voltage, and temperature variations. In the proposed approach, the sliding-mode controller (SMC) is implemented digitally; utilizing a first order single-bit ΣΔ frequency to digital converter (ΣΔFDC)-based feedback and reference digitizing ADCs, running at 32-MHz sampling rate. The ADSM regulator achieves 1% settling time in less than 5 μs for a load variation of 600 mA. The SMC uses a high-bandwidth hysteretic differentiator and an integrator to perform the sliding control law in digital domain. The proposed approach overcomes the steady-state error (or dc offset), and band limits the switching frequency, which are the two common problems associated with SMCs. The IC is designed and fabricated on a 0.35-μm CMOS process occupying an active area of 2.72 mm 2 .
