The first Medipix chip which aimed at permitting single photon counting on a sizable matrix of pixels was developed in the mid-1990's. In the following 20 years two families of chips have evolved ...from that initial effort. The Medipix photon counting family of chips comprises Medipix, Medipix2 and Medipix3. A 4th generation chip, Medipix4, is under development. The Timepix chips were initially more aimed at single particle detection and that family comprises Timepix, the most recent Timepix2 chip (introduced in this Special Issue) and Timepix3. The 4th generation Timepix4 is also under development and a first version will be produced in 2019. This paper seeks to provide a brief introduction to the various members of the Medipix family and provide references to more detailed descriptions already available in the literature.
A novel approach for the readout of a TPC at the future linear collider is to use a CMOS pixel detector combined with some kind of gas gain grid. A first test using the photon counting chip Medipix2 ...with GEM or Micromegas demonstrated the feasibility of such an approach. Although this experiment demonstrated that single primary electrons could be detected the chip did not provide information on the arrival time of the electron in the sensitive gas volume nor did it give any indication of the quantity of charge detected. The Timepix chip uses an external clock with a frequency of up to 100
MHz as a time reference. Each pixel contains a preamplifier, a discriminator with hysteresis and 4-bit DAC for threshold adjustment, synchronization logic and a 14-bit counter with overflow control. Moreover, each pixel can be independently configured in one of four different modes: masked mode: pixel is off, counting mode: 1-count for each signal over threshold, TOT mode: the counter is incremented continuously as long as the signal is above threshold, and arrival time mode: the counter is incremented continuously from the time the first hit arrives until the end of the shutter. The chip resembles very much the Medipix2 chip physically and can be readout using slightly modified versions of the various existing systems. This paper presents the main features of the new design, electrical measurements and some first images.
Medipix3 is a 256×256 channel hybrid pixel detector readout chip working in a single photon counting mode with a new inter-pixel architecture, which aims to improve the energy resolution in pixelated ...detectors by mitigating the effects of charge sharing between channels. Charges are summed in all 2×2 pixel clusters on the chip and a given hit is allocated locally to the pixel summing circuit with the biggest total charge on an event-by-event basis. Each pixel contains also two 12-bit binary counters with programmable depth and overflow control. The chip is configurable such that either the dimensions of each detector pixel match those of one readout pixel or detector pixels are four times greater in area than the readout pixels. In the latter case, event-by-event summing is still possible between the larger pixels. Each pixel has around 1600 transistors and the analog static power consumption is below 15
μW in the charge summing mode and 9
μW in the single pixel mode. The chip has been built in an 8-metal 0.13
μm CMOS technology. This paper describes the chip from the pixel to the periphery and first electrical results are summarized.
This manuscript describes the optimization of the front-end readout electronics for high granularity hybrid pixel detectors. The theoretical study aims at minimizing the noise and jitter. The model ...presented here is validated with both circuit post layout simulations and measurements on the Timepix4 Application Specific Integrated Circuit (ASIC). The analog front-end circuit and the procedure to optimize the dimensions of the main transistors are described with detail.
The Timepix4 is the most recent ASIC designed in the framework of the Medipix4 Collaboration. It was manufactured in 65nm CMOS process, and consists of a four side buttable matrix of 448 × 512 pixels with 55µm pitch. The analog front-end has a gain of ∼36mV/ke- when configured in High Gain Mode, and ∼20mV/ke- when configured in Low Gain Mode. The Equivalent Noise Charge (ENC) is ∼68e-rms and ∼80e-rms in High Gain Mode and in Low Gain Mode respectively. In event driven mode the incoming hits can be time stamped within a ∼ 200ps time bin and the chip can deal with a maximum flux of ∼ 3.6MHzmm−2s−1. In photon counting mode, the chip can deal with up to ∼ 5GHzmm−2s−1.
The routine designed to optimize the Timepix4 front-end is then used to analyze the performance limits in terms of jitter and noise for Charge Sensitive Amplifiers in pixel detectors.
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