Full-duplex bidirectional transmission at 10 Gb/s is demonstrated for extended wavelength division multiplexed passive optical network (WDM-PON) applications, achieving transmission distances up to ...25 km of standard single mode fiber (SSMF) when using a low-bandwidth (approximately 1.2 GHz) reflective semiconductor optical amplifier (RSOA) for signal re-modulation at the optical network unit (ONU). The system is assisted by optimum offset filtering at the optical line terminal (OLT)-receiver and the performance is further improved with the use of decision-feedback equalization (DFE). Chromatic dispersion (CD) and Rayleigh Backscattering (RB) effects are considered and analyzed.
In this paper, the optimum design characteristics and the transmission performance limits of an intensity modulation full-duplex bidirectional transmission system at 10 Gb/s are experimentally ...studied and presented for application in next-generation-extended wavelength-division-multiplexed passive optical networks. A low-bandwidth (~1.2 GHz) reflective semiconductor optical amplifier (RSOA) is utilized at the optical network unit (ONU) site of the system. Its remodulation properties and performance are examined for both continuous wave and modulated downstream signal, stemming from the optical line terminal (OLT). The techniques adopted to optimize performance are: 1) the use of detuned optical filtering at the OLT receiver that takes advantage of the RSOA chirp and 2) the use of decision feedback equalization (DFE). The extinction ratio of the downstream signal and the driving operation point of the RSOA are examined experimentally in order to find the optimum conditions for the bidirectional transmission. Moreover, the impact of patterning effects in the performance of the system is evaluated. Finally, the additional performance improvement that is achieved with the use of DFE technique is shown.
The transmission performance improvement of low-cost conventional directly modulated laser (DML) sources, fabricated for operation at 2.5 Gb/s but modulated at 10 Gb/s is presented and experimentally ...demonstrated. Performance improvement is achieved by electronic feed-forward and decision-feedback equalization as well as offset optical filtering at the receiver end. Experimental studies consider both transient and adiabatic chirp dominated DML sources. The transmission improvement is evaluated in terms of required optical signal-to-noise ratio (OSNR) for bit-error-rate values of 10 -9 versus transmission length over uncompensated links of standard single-mode fiber (SSMF). Additionally, the optimum filter position is examined in combination with equalization and in terms of OSNR versus detuning from the center wavelength.
A 64/spl times/64-pixel image sensor with full-frame analog memory and on-chip motion processor is presented. The processor consists of a charge amplifier and an analog subtractor. It uses the ...switched-capacitor technique and calculates the difference between the values of the signal on each pixel in successive frames. The rate can achieve up to 60 frames/s with limited area and power overhead. The analog memory required for the storage of the previous frame is implemented using implanted capacitors placed within the sensor array. Fabricated in a 1.2-/spl mu/m standard CMOS process with an added metal 3 light-shielding layer, the circuit is fully functional and requires a total core area of 13 mm/sup 2/.< >
In optical (charge) amplifier design, it is common practice, to size the input MOSFET so that the amplifier's input capacitance is approximately equal to the value of the photodiode capacitance. When ...plotted versus capacitance, the input equivalent noise current reaches its minimum value, for a given drain bias current, in a curve widely known and characterized as a shallow one. For high bit rate photocurrent amplifiers, which employ short-channel MOSFET's as the input device, the observed sensitivity degradation is due to the increased input referred noise attributed to the MOSFET's short-channel operation. It is shown here that for short-channel MOSFET's the electron warming in the channel, the voltage fluctuations due to the gate polysilicon resistance, and the induced thermal noise at the gate, lead to a considerably lower value for the optimum input capacitance. In this case, the noise power versus the capacitance curve becomes steeper and the minimum is more prominent.
We present a fully integrated differential distributed voltage-controlled oscillator implemented in a 0.35-mum SiGe BiCMOS technology. The delay variation by a positive feedback tuning technique, ...adopted from the ring oscillators, is demonstrated as a fine-tuning alternative, which results to an approximately 420-MHz tuning range. The phase noise is -98 dBc/Hz at 1-MHz offset from the 14.25-GHz carrier. An integrated output buffer isolates the oscillator from the measurement equipment. The measured output power is -17.5 dBm and the overall power consumption of the chip is 138.1 mW employing two power supplies of 3.2 and 4.2 V, respectively
Thermal noise modeling for short-channel MOSFETs Triantis, D.P.; Birbas, A.N.; Kondis, D.
IEEE transactions on electron devices,
1996-Nov., 1996-11-00, 19961101, Letnik:
43, Številka:
11
Journal Article
Recenzirano
An analytical formulation of the thermal noise in short-channel MOSFETs, working in the saturation region, is presented. For the noise calculation, we took into account effects like the field ...dependent noise temperature and mobility, the device geometry and the channel length modulation, the back gate effect and the velocity saturation. The derived data from the model are in good agreement with reported thermal noise measurements, regarding the noise bias dependence, for transistors with channel lengths shorter than 1 /spl mu/m. Since the present thermal noise models of MOS transistors are valid for channel lengths well above 1 /spl mu/m, the proposed model can be easily incorporated in circuit simulators like SPICE, providing an extension to the analytical thermal noise modeling suitable for submicron MOSFETs.
Although recent implementations of analog iterative decoders have proven their potential for higher decoding speed and less power consumption than their digital counterparts, the CMOS or conventional ...BiCMOS technologies used so far seem to be incapable to cope with the need for high throughput that high-speed applications require. Within this context this work presents the design and test results of a high-speed analog SISO (Soft-Input Soft-Output) channel decoder for an 8-bit trellis code by exploiting the high-speed features of SiGe heterojunction bipolar transistors (HBTs). It is one of the first successful implementations of an error-correcting decoder in SiGe BiCMOS technology, which incorporates a high-speed I/O interface. A high-level model of the mismatch effects indicates that there is no significant performance penalty. Moreover, simulations and performance evaluations of an analog Turbo decoder based on the designed SISO decoder are provided. Even though the IC of the SISO module was tested at a throughput up to 3 Mbps, simulation results show that the decoder is capable to operate at 50 Mbps. The measured power consumption is 860 mW and the die area is 3.4 X 3 mm.
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