An asynchronous A/D Converter architecture based on a binary tree structure is presented in this paper. Two alternative design strategies are presented that lead either to a high mismatch immunity ...ADC that requires a light calibration logic (area: 0.123mm2, power: 72mW) or a faster, tinier and even lower power ADC (area: 0.21mm2, power: 25mW) with lower mismatch immunity that needs a slightly more complicated calibration logic. Both alternative ADC design strategies require at least one or two orders of magnitude lower area than any known approach and a remarkable low power consumption without sacrificing speed. The designed A/D Converter can operate with a configurable resolution of either 4, 8, or 12-bits. Moreover, 6 quaternary digits or three 16-level outputs are also available from the intermediate nodes of the binary tree, for applications that require multi-valued communication lines. Simulation results prove that the peak conversion rate of the high mismatch immunity A/D design alternative exceeds 300, 230 and 225MS/s for 4, 8 and 12-bit resolution, respectively, while the peak conversion rate of the faster design alternative is higher than 500, 440 and 420MS/s for 4, 8 and 12-bit resolution, respectively. An appropriate sample/hold and voltage to current conversion architecture has been developed along with an intelligent output latching technique that improve the achieved signal to noise and distortion ratio by up to 7dB. Moreover, an appropriate calibration method that extends the temperature operating range and compensates for the component mismatches is presented. The ultra low area and power consumption of the developed ADC architecture favours its employment in sensor networks while these features make its use attractive as a building block in time interleaved parallel ADCs for the achievement of ultra high speed conversion.
This paper presents a hardware/software co-design approach where different specification languages can be used in parallel, allowing effective system co-modeling. The proposed methodology introduces ...a process model that extends the traditional spiral model so as to reflect the design needs of modern embedded systems. The methodology is supported by an advanced toolset that allows co-modeling and co-simulation using SDL, Statecharts and MATRIXX, and interactive hardware/software partitioning. The effectiveness of the proposed approach is exhibited through two application examples: the design of a car window lift mechanism, and the design of a MAC layer protocol for wireless ATM networks.
High-energy cosmic rays are one of the primary sources of information for scientists investigating the elementary properties of matter. The need to study cosmic rays, with energies thousands of times ...larger than those encountered in particle accelerators, led to the development of modern detection hardware and experimental methodologies. We present a low power, low complexity data acquisition (DAQ) system with 100 ps resolution, suitable for particle and radiation detection experiments. The system uses a Multiple-Time-over-Threshold (MToT) technique for the treatment of the output signal of Photo Multiplier Tubes (PMTs). The use of three thresholds compensates for the slewing effects and offers a more accurate measurement of the PMT pulses' width. For the evaluation of the pulse the system uses comparators and a Time-to-Digital (TDC) converter, whereas the pulses are time-stamped using the GPS signal. The prototype card is analyzed for its noise behavior and is tested to verify its performance. The system has been designed for the HEllenic LYceum Cosmic Observatories Network (HELYCON) Extensive Air Showers (EAS) detector.
The wide band noise voltage (equivalent thermal noise voltage at the gate) of a submicron MOSFET, working in saturation, exhibits a minimum value at a certain drain current. This is supported by ...measurements and theoretical analysis based on a suitable thermal noise model. This macroscopic noise model attributes the thermal noise of the drain current to the superposition of two noise sources originating from two separate regions of the transistor's channel (a gradual channel approximation region and a saturation region). The existence of a minimum of the noise spectral density at an optimum drain current (I/sub opt/), is well proved by measurements and is contradictory to the predictions of the current simulation program with integrated circuit emphasis (SPICE) models. An empirical way for evaluating analytically I/sub opt/ is given. The fact of the existence of a noise minimum for a submicron MOSFET, brings a phenomenological equivalence to the bipolar transistor and GaAs MESFET when they are employed at the first stage of an amplifier.
This article presents the design and development of a networking system architecture targeted to support high-speed TCP/IP communication over ATM. The discussed architecture has been developed in the ...form of an integrated system which incorporates state-of-the-art software and hardware subsystems, and an OC-12c ATM adapter (622 Mb/s). Moreover, the design of this embedded system has been based on the Chorus real-time operating system, which, in turn, hosts an accelerated TCP/IP protocol stack over ATM. Furthermore, the embedded system board has been developed according to the PCI specification to easily be plugged into a host platform. In addition, the OC-12c ATM adapter subsystem has been designed and developed in order to also be plugged into the same host. The developed architecture has proven very efficient and reliable, providing high-throughput and low-latency bulk data communications. The measured performance on an OC-3c-based (155 Mb/s) testbed has shown that an optimally implemented TCP/IP stack, hosted by a real-time kernel and coupled with an ATM adapter, offers a robust desktop platform for high-speed end-to-end communications. The main feature of the accelerated TCP/IP protocol stack is the out-of-band processing of control and data information. The protocol accelerator embedded system processes the TCP/IP headers and accomplishes checksum computations, while data is transferred from the host's user memory space directly to the network. Finally, for validation purposes, the prototype system has been incorporated in an existing networking infrastructure targeted to support mass storage applications.
