This paper presents the radiation testing of a commercial-off-the-shelf SRAM-based field-programmable gate arrays (FPGAs) with heavy ions. Test experiments have been conducted to identify and to ...classify the single-event upsets (SEUs) in the configuration memory that induce single-event functional interrupt for the user-implemented circuit. Moreover the paper presents a new approach for assessing the effects of SEUs based on the combination of radiation testing and simulation-based fault injection tool. First experimental results show the FPGA look-up table (LUT) resources (used to implement combinatorial logic) are the most sensitive to SEUs, whereas interconnect resources are the most critical for the device cross section because they use the largest number of configuration bits. The analysis of experimental data underlines that the most probable error affecting interconnections is the shorting of two nets. This observation indicates that new fault models should be considered along with the classic stuck-at one model designing fault-tolerant architectures, which are intended for implementation in FPGA devices.
Hardening SoCs against transient faults requires new techniques able to combine high fault detection capabilities with the usual requirements of SoC design flow, e.g., reduced design-time, low area ...overhead, and reduced (or null) accessibility to source core descriptions. This paper proposes a new hybrid approach which combines hardening software transformations with the introduction of an Infrastructure IP with reduced memory and performance overheads. The proposed approach targets faults affecting the memory elements storing both the code and the data, independently of their location (inside or outside the processor). Extensive experimental results, including comparisons with previous approaches, are reported, which allow practically evaluating the characteristics of the method in terms of fault detection capabilities and area, memory, and performance overheads.
Hardware designers need effective techniques for early evaluation of the hardening mechanisms adopted in safety-critical VLSI circuits. We propose field-programmable gate-array based circuit ...emulation for performing fault-injection campaigns. Experimental results show that the new technique is about four orders of magnitude faster than simulation-based fault injection.
SRAM-based field programmable gate arrays (FPGAs) are particularly sensitive to single event upsets (SEUs) that, by changing the FPGA's configuration memory, may affect dramatically the functions ...implemented by the device. In This work we describe a new approach for predicting SEU effects in circuits mapped on SRAM-based FPGAs that combines radiation testing with simulation. The former is used to characterize (in terms of device cross section) the technology on which the FPGA device is based, no matter which circuit it implements. The latter is used to predict the probability for a SEU to alter the expect behavior of a given circuit. By combining the two figures, we then compute the cross section of the circuit mapped on the pre-characterized device. Experimental results are presented that compare the approach we developed with a traditional one based on radiation testing only, to measure the cross section of a circuit mapped on an FPGA. The figures here reported confirm the accuracy of our approach.
In this paper, two low-cost solutions devoted to provide processor-based systems with error-detection capabilities are compared. The effects of single event upsets (SEUs) and single event transients ...(SETs) are studied through simulation-based fault injection. The error-detection capabilities of a hardware-implemented solution based on parity code are compared with those of a software-implemented solution based on source-level code modification. Radiation testing experiments confirmed results obtained by simulation.
A large part of microprocessor cores in use today are designed to be cheap and mass produced. The diagnostic process, which is fundamental to improve yield, has to be as cost effective as possible. ...This paper presents a novel approach to the construction of diagnosis-oriented software-based test sets for microprocessors. The methodology exploits existing manufacturing test sets designed for software-based self-test and improves them by using a new diagnosis-oriented approach. Experimental results are reported in this paper showing the feasibility, robustness, and effectiveness of the approach for diagnosing stuck-at faults on an Intel i8051 processor core.
Cache memories embedded in most of complex processors significantly contribute to the global single event upset-induced error rate. Three different approaches allowing the study of this contribution ...by fault injection are investigated in this paper.
This paper deals with a software modification strategy allowing on-line detection of transient errors. Being based on a set of rules for introducing redundancy in the high-level code, the method can ...be completely automated, and is therefore particularly suited for low-cost safety-critical microprocessor-based applications. Experimental results are presented and discussed, demonstrating the effectiveness of the approach in terms of fault detection capabilities.
A pipelined processor with a high-level behavioral HDL description is presented in this paper. It generates a set of effective test programs by using a simulator, which is able to evaluate with ...respect to an RTL coverage metric. The proposed optimizer is based on a technique called microGP, an evolutionary system able to automatically device and optimizes the program written in an assembly language. Quantitative coverage measurement presented will guide the test-program generation. The approach is fully automatic and broadly applicable. The minimal test set with the programmable coverage is attained.
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