The associative memory (AM) system of fast tracker (FTK) processor has been designed for the tracking trigger upgrade to the ATLAS detector at the Conseil Europeen Pour La Recherche Nucleaire large ...hadron collider. The system performs pattern matching (PM) using the detector hits of particles in the ATLAS silicon tracker. The AM system is the main processing element of FTK and is mainly based on the use of application-specified integrated circuits (ASICs) (AM chips) designed to execute PM with a high degree of parallelism. It finds track candidates at low resolution which become seeds for a full resolution track fitting. The AM system implementation is based on a collection of large 9U Versa Module Europa (VME) boards, named "serial link processors" (AMBSLPs). On these boards, a huge traffic of data is implemented on a network of 900 2-Gb/s serial links. The complete AM-based processor consumes much less power (~50 kW) than its CPU equivalent and its size is much smaller. The AMBSLP has a power consumption of ~250 W and there will be 16 of them in a crate. This results in unusually large power consumption for a VME crate and the need for complex custom infrastructure in order to have sufficient cooling. This paper reports on the design and testing of the infrastructures needed to run and cool the system which will include 16 AMBSLPs in the same crate, the integration of the AMBSLP inside a first FTK slice, the performance of the produced prototypes (both hardware and firmware), as well as their tests in the global FTK integration. This is an important milestone to be satisfied before the FTK production.
A cognitive image processing implementation for pattern-matching execution is proposed in this paper. It is based on the learning process of the human vision as an edge-enhancing filter for medical ...images. We set up an experiment to test its impact on the performance of decision-making algorithm working on brain magnetic resonance data. The execution times of similar filters can become unpractical on real 3-D or higher dimensional data, if implemented on a CPU. An innovative and high-performance embedded system for real-time pattern matching was developed. The design uses field-programmable gate arrays and the powerful associative memory chip (an ASIC) to achieve real-time performance and requires a training phase and a data acquisition phase. It is a very compact implementation that improves execution time ×1000 for the training phase and ×100 for the data acquisition phase for 2-D black and white images compared to a last generation i7 CPU. The implementation of this edge-enhancing filter is expected to positively impact on medical devices for real-time diagnosis (e.g., diagnostic ultrasound) and for image processing steps in medical image analysis where computing power is a limiting factor.
A multi-core FPGA-based 2D-clustering implementation for real-time image processing is presented in this paper. The clustering algorithm is using a moving window technique to reduce the time and data ...required for the cluster identification process. The implementation is fully generic, with an adjustable detection window size. A fundamental characteristic of the implementation is that multiple clustering cores can be instantiated. Each core can work on a different identification window that processes data of independent "images" in parallel, thus, increasing performance by exploiting more FPGA resources. The algorithm and implementation are developed for the Fast TracKer processor for the trigger upgrade of the ATLAS experiment but their generic design makes them easily adjustable to other demanding image processing applications that require real-time pixel clustering.
A high-performance "pattern matching" implementation based on the Associative Memory (AM) system is presented. It is designed to solve the real-time hit-to-track association problem for particles ...produced in high-energy physics experiments at hadron colliders. The processing time of pattern recognition in CPU-based algorithms increases rapidly with the detector occupancy due to the limited computing power and input-output capacity of hardware available on the market. The AM system presented here solves the problem by being able to process even the most complex hadron collider events produced at a rate of 100 kHz with an average latency smaller than 10 μs. The board built for this goal is able to execute ~12 petabyte comparisons per second, with peak power consumption below 250 W, uniformly distributed on the large area of the board.
High performance embedded system for real-time pattern matching Sotiropoulou, C.-L.; Luciano, P.; Gkaitatzis, S. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
02/2017, Letnik:
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In this paper we present an innovative and high performance embedded system for real-time pattern matching. This system is based on the evolution of hardware and algorithms developed for the field of ...High Energy Physics and more specifically for the execution of extremely fast pattern matching for tracking of particles produced by proton–proton collisions in hadron collider experiments. A miniaturized version of this complex system is being developed for pattern matching in generic image processing applications. The system works as a contour identifier able to extract the salient features of an image. It is based on the principles of cognitive image processing, which means that it executes fast pattern matching and data reduction mimicking the operation of the human brain. The pattern matching can be executed by a custom designed Associative Memory chip. The reference patterns are chosen by a complex training algorithm implemented on an FPGA device. Post processing algorithms (e.g. pixel clustering) are also implemented on the FPGA. The pattern matching can be executed on a 2D or 3D space, on black and white or grayscale images, depending on the application and thus increasing exponentially the processing requirements of the system. We present the firmware implementation of the training and pattern matching algorithm, performance and results on a latest generation Xilinx Kintex Ultrascale FPGA device.
•A high performance embedded system for real-time pattern matching is proposed.•It is based on a system developed for High Energy Physics experiment triggers.•It mimics the operation of the human brain (cognitive image processing).•The process can be executed on 2D and 3D, black and white or grayscale images.•The implementation uses FPGAs and custom designed associative memory (AM) chips.
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