The low communication bandwidth between memory and processing units in conventional von Neumann machines does not support the requirements of emerging applications that rely extensively on large sets ...of data. More recent computing paradigms, such as high parallelization and near‐memory computing, help alleviate the data communication bottleneck to some extent, but paradigm‐shifting concepts are required. In‐memory computing has emerged as a prime candidate to eliminate this bottleneck by colocating memory and processing. In this context, resistive switching (RS) memory devices is a key promising choice, due to their unique intrinsic device‐level properties, enabling both storing and computing with a small, massively‐parallel footprint at low power. Theoretically, this directly translates to a major boost in energy efficiency and computational throughput, but various practical challenges remain. A qualitative and quantitative analysis of several key existing challenges in implementing high‐capacity, high‐volume RS memories for accelerating the most computationally demanding computation in machine learning (ML) inference, that of vector‐matrix multiplication (VMM), is presented. The monolithic integration of RS memories with complementary metal–oxide–semiconductor (CMOS) integrated circuits is presented as the core underlying technology. The key existing design choices in terms of device‐level physical implementation, circuit‐level design, and system‐level considerations is reviewed and an outlook for future directions is provided.
The design considerations, challenges, and perspectives are discussed and recent advances in monolithically integrated complementary metal–oxide–semiconductor (CMOS)‐resistive switching (RS) memory vector‐matrix multiplication (VMM) hardware for accelerating modern neural network applications are elucidated. It devises a new perspective on the physical constraints, circuit‐level limitations, along with design flow for input and output circuits, and explains system‐level challenges and opportunities for these hardware platforms.
Novel computing architectures based on resistive switching memories (also known as memristors or RRAMs) have been shown to be promising approaches for tackling the energy inefficiency of deep ...learning and spiking neural networks. However, resistive switch technology is immature and suffers from numerous imperfections, which are often considered limitations on implementations of artificial neural networks. Nevertheless, a reasonable amount of variability can be harnessed to implement efficient probabilistic or approximate computing. This approach turns out to improve robustness, decrease overfitting and reduce energy consumption for specific applications, such as Bayesian and spiking neural networks. Thus, certain non-idealities could become opportunities if we adapt machine learning methods to the intrinsic characteristics of resistive switching memories. In this short review, we introduce some key considerations for circuit design and the most common non-idealities. We illustrate the possible benefits of stochasticity and compression with examples of well-established software methods. We then present an overview of recent neural network implementations that exploit the imperfections of resistive switching memory, and discuss the potential and limitations of these approaches.
•Extraction of stress profiles in AlGaN and GaN layers from in-situ bow measurement.•Good matching between extracted profiles and XRD measurements.•Maximum stress from in-situ bow is correlated to ...dislocation density.
We have analyzed the in-situ measurements of bow and reflectance during growth of GaN on silicon layers for HEMT based devices, varying the quality of the layers by changing the AlN nucleation layer. By fitting the curves and applying the Stoney equation, we were able to extract stress profiles in the layers, and convert these into out of plane strain profiles. This allowed us to simulate X-Ray Diffraction profiles which matched well with measured data, confirming the validity of our data extraction. Finally, we see that we incorporate less stress with a higher dislocation density in the GaN layers, and so for a given set of growth conditions, we can infer the dislocation density by looking at the relaxation rate.
X‐Ray diffraction microstrain characterization is a technique which enables the quantification of threading dislocations by measuring the radial microstrain field surrounding these defects. This work ...demonstrates how to accurately perform these measurements on a broad range of GaN samples. In particular, for GaN grown on Si substrates with large stress gradient through the layer, the measurements need to be performed on the (20–25) reflection to avoid being affected by a macrostrain influence. A comparison of this characterization with cathodoluminescence and X‐ray diffraction lattice misorientations measurements shows differences in the measurement depth, so the results are affected by the various evolutions of dislocations densities through the layers of the different samples. Independently of the measurement depth, the analysis also highlights a dependence of the X‐ray measurements results on the type of sample, in particular the starting substrate. Microstrain measurements appear therefore as being well suited for the comparison of threading dislocations densities between similar GaN layers. It can be used to replace lattice misorientations measurements, or be associated with them to obtain an edge versus screw dislocations ratio.
This work presents an X‐ray diffraction measurement of threading dislocations densities, based on the surrounding microstrain field analysis. It demonstrates how to accurately characterize different gallium nitride samples, including specimens grown on silicon substrates with large stress gradient through the layer. A comparison between microstrain, lattice misorientations, and cathodoluminescence measurements highlights the potential and the issues of this technique.
•Ga pollution in CCS reactor strongly affects the growth process stability of InGaN.•Ga pollution decreases In incorporation and increases InGaN layer thickness.•Clean CCS reactor chamber reduces the ...degree of complexity in InGaN MOVPE growth.
We show that gallium pollution in an AIXTRON Close Coupled Showerhead (CCS) Metal-Organic Vapor Phase Epitaxy (MOVPE) reactor can strongly affect the growth process stability of InGaN layers. By comparing growth with and without gallium pollution from the showerhead, we find a decrease in the indium incorporation and an increase in layer thickness of up to three times when the pollution is present. This phenomenon varies with the quantity of gallium on the showerhead, with increased gallium due to thicker GaN growth causing a stronger effect. Higher TMIn flows also give a more pronounced effect. These data support our previous hypothesis of TMIn reacting with metallic gallium present on the showerhead surface to release TMGa, which is then incorporated as Ga into the grown layers. This study of the effect of gallium contamination on InGaN layers in CCS MOVPE reactors leads us to suggest that the growth in CCS reactors should be performed free from gallium pollution to give more stable and comprehensible results.
Abstract
A key challenge in scaling quantum computers is the calibration and control of multiple qubits. In solid-state quantum dots (QDs), the gate voltages required to stabilize quantized charges ...are unique for each individual qubit, resulting in a high-dimensional control parameter space that must be tuned automatically. Machine learning techniques are capable of processing high-dimensional data—provided that an appropriate training set is available—and have been successfully used for autotuning in the past. In this paper, we develop extremely small feed-forward neural networks that can be used to detect charge-state transitions in QD stability diagrams. We demonstrate that these neural networks can be trained on synthetic data produced by computer simulations, and robustly transferred to the task of tuning an experimental device into a desired charge state. The neural networks required for this task are sufficiently small as to enable an implementation in existing memristor crossbar arrays in the near future. This opens up the possibility of miniaturizing powerful control elements on low-power hardware, a significant step towards on-chip autotuning in future QD computers.
Mining big data to make predictions or decisions is the main goal of modern artificial intelligence (AI) and machine learning (ML) applications. Vast innovation in algorithms, their software ...implementations and data management has enabled great progress to date, but wide adoption has been slowed by limited capabilities of existing computing hardware. The low communication bandwidth between memory and processing units in conventional von Neumann machines does not support the requirements of emerging applications that rely extensively on large sets of data. More recent computing paradigms, such as high parallelization and near-memory computing (e.g., in GPUs) help alleviate the data communication bottleneck to some extent, but paradigm-shifting concepts are required. In-memory computing has emerged as a prime candidate to eliminate this bottleneck by co-locating the memory and processing. In this context, resistive switching (RS) memory devices is a key promising choice, due to their unique intrinsic device-level properties enabling both storing and computing with a small, massively-parallel footprint at a low power. Theoretically, this directly translates to a major boost in energy efficiency and computational throughput, but various practical challenges remain. We present a qualitative and quantitative analysis of several key existing challenges in implementing high-capacity, high-volume RS memories for accelerating the most computationally demanding computation in ML inference – that of vector-matrix multiplication (VMM). Monolithic integration of RS memories with CMOS integrated circuits is presented as the core underlying technology. We review key existing design choices in terms of device-level physical implementation, circuit-level design, and system-level considerations, and provide an outlook for future directions.
Neural decoders for quantum error correction (QEC) rely on neural networks to classify syndromes extracted from error correction codes and find appropriate recovery operators to protect logical ...information against errors. Despite the good performance of neural decoders, important practical requirements remain to be achieved, such as minimizing the decoding time to meet typical rates of syndrome generation in repeated error correction schemes, and ensuring the scalability of the decoding approach as the code distance increases. Designing a dedicated integrated circuit to perform the decoding task in co-integration with a quantum processor appears necessary to reach these decoding time and scalability requirements, as routing signals in and out of a cryogenic environment to be processed externally leads to unnecessary delays and an eventual wiring bottleneck. In this work, we report the design and performance analysis of a neural decoder inference accelerator based on an in-memory computing (IMC) architecture, where crossbar arrays of resistive memory devices are employed to both store the synaptic weights of the decoder neural network and perform analog matrix-vector multiplications during inference. In proof-of-concept numerical experiments supported by experimental measurements, we investigate the impact of TiO\(_\textrm{x}\)-based memristive devices' non-idealities on decoding accuracy. Hardware-aware training methods are developed to mitigate the loss in accuracy, allowing the memristive neural decoders to achieve a pseudo-threshold of \(9.23\times 10^{-4}\) for the distance-three surface code, whereas the equivalent digital neural decoder achieves a pseudo-threshold of \(1.01\times 10^{-3}\). This work provides a pathway to scalable, fast, and low-power cryogenic IMC hardware for integrated QEC.
This study presents a machine-learning-based procedure to automate the charge tuning of semiconductor spin qubits with minimal human intervention, addressing one of the significant challenges in ...scaling up quantum dot technologies. This method exploits artificial neural networks to identify noisy transition lines in stability diagrams, guiding a robust exploration strategy leveraging neural networks' uncertainty estimations. Tested across three distinct offline experimental datasets representing different single quantum dot technologies, the approach achieves over 99% tuning success rate in optimal cases, where more than 10% of the success is directly attributable to uncertainty exploitation. The challenging constraints of small training sets containing high diagram-to-diagram variability allowed us to evaluate the capabilities and limits of the proposed procedure.
Passive resistive random access memory (ReRAM) crossbar arrays, a promising emerging technology used for analog matrix-vector multiplications, are far superior to their active (1T1R) counterparts in ...terms of the integration density. However, current transfers of neural network weights into the conductance state of the memory devices in the crossbar architecture are accompanied by significant losses in precision due to hardware variabilities such as sneak path currents, biasing scheme effects and conductance tuning imprecision. In this work, training approaches that adapt techniques such as dropout, the reparametrization trick and regularization to TiO2 crossbar variabilities are proposed in order to generate models that are better adapted to their hardware transfers. The viability of this approach is demonstrated by comparing the outputs and precision of the proposed hardware-aware network with those of a regular fully connected network over a few thousand weight transfers using the half moons dataset in a simulation based on experimental data. For the neural network trained using the proposed hardware-aware method, 79.5% of the test set's data points can be classified with an accuracy of 95% or higher, while only 18.5% of the test set's data points can be classified with this accuracy by the regularly trained neural network.
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