A spiking neural network (SNN) inspired by the structure and principles of the human brain can significantly enhance the energy efficiency of artificial intelligence computing by overcoming the ...bottlenecks of the conventional von Neumann architecture with its massive parallelism and spike transmissions. The construction of artificial neurons is important for the hardware implementation of an SNN, which generates spike signals when enough synaptic signals are gathered. Because circuit‐level artificial neurons with comparator and reset circuits require considerable hardware area, intensive efforts are devoted in recent years for building artificial neurons at the device level for better area efficiency. Furthermore, artificial sensory neuron devices, which perform neural processing and sensing concurrently, have recently been developed in order to reduce the hardware cost and energy consumption of traditional sensory systems through in‐sensor computing. This review article surveys and benchmarks the recent progress of artificial neuron devices for neural processing and sensing. First, various artificial neuron devices are summarized, including single‐transistor neurons (1T‐neurons), memristor neurons, phase‐change neurons, magnetic neurons, and ferroelectric neurons. Next, cointegration technologies with artificial synaptic devices and artificial sensory neurons for in‐sensor computing are introduced. Finally, the challenges and prospects for developing artificial neuron devices are discussed.
The recent progress in artificial neuron devices for neural processing and sensing in a bioinspired spiking neural network is reviewed. Various artificial neuron devices with spiking operation, corresponding cointegration technologies with artificial synaptic devices, and recently emerging artificial sensory neurons for low‐power in‐sensor computing are addressed.
Neuromorphic hardware computing is a promising alternative to von Neumann computing by virtue of its parallel computation and low power consumption. To implement neuromorphic hardware based on deep ...neural network (DNN), a number of synaptic devices should be interconnected with neuron devices. For ideal hardware DNN, not only scalability and low power consumption, but also a linear and symmetric conductance change with a large number of conductance levels is required. Here, an all‐solid‐state polymer electrolyte‐gated synaptic transistor (pEGST) is fabricated on an entire silicon wafer with CMOS microfabrication and initiated chemical vapor deposition process. The pEGST shows good linearity as well as symmetry in potentiation and depression, conductance levels up to 8,192, and low switching energy smaller than 20 fJ pulse−1. Selected 128 levels from 8,192 are used to identify handwritten digits in the MNIST database with the aid of a multilayer perceptron, resulting in a recognition rate of 91.7%.
An all‐solid‐state polymer electrolyte‐gated synaptic transistor (pEGST) is fabricated on an entire silicon wafer with CMOS microfabrication and initiated chemical vapor deposition process. The pEGST shows good linearity as well as symmetry in potentiation and depression, conductance levels up to 8,192, and low switching energy smaller than 20 fJ pulse−1.
An ion‐based synaptic transistor (synaptor) is designed to emulate a biological synapse using controlled ion movements. However, developing a solid‐state electrolyte that can facilitate ion movement ...while achieving large‐scale integration remains challenging. Here, a bio‐inspired organic synaptor (BioSyn) with an in situ ion‐doped polyelectrolyte (i‐IDOPE) is demonstrated. At the molecular scale, a polyelectrolyte containing the tert‐amine cation, inspired by the neurotransmitter acetylcholine is synthesized using initiated chemical vapor deposition (iCVD) with in situ doping, a one‐step vapor‐phase deposition used to fabricate solid‐state electrolytes. This method results in an ultrathin, but highly uniform and conformal solid‐state electrolyte layer compatible with large‐scale integration, a form that is not previously attainable. At a synapse scale, synapse functionality is replicated, including short‐term and long‐term synaptic plasticity (STSP and LTSP), along with a transformation from STSP to LTSP regulated by pre‐synaptic voltage spikes. On a system scale, a reflex in a peripheral nervous system is mimicked by mounting the BioSyns on various substrates such as rigid glass, flexible polyethylene naphthalate, and stretchable poly(styrene‐ethylene‐butylene‐styrene) for a decentralized processing unit. Finally, a classification accuracy of 90.6% is achieved through semi‐empirical simulations of MNIST pattern recognition, incorporating the measured LTSP characteristics from the BioSyns.
A high‐performance solid‐state electrolyte containing mobile tert‐amine cations is designed and synthesized. The electrolyte to modulate synaptic weights is deposited and doped simultaneously with iCVD, using an in situ process that permits large‐scale integration. Bio‐inspired organic synaptic transistors are fabricated on rigid, flexible, and stretchable substrates. Short‐ and long‐term synaptic plasticity and their transformability are verified.
For the first time, a leaky integrate-and-fire (LIF) neuron with both excitatory and inhibitory characteristics is demonstrated using a single MOSFET. No additional circuits such as comparator, reset ...circuit, or current-to-voltage converter as well as a membrane capacitor are needed, and thus the LIF neuron is realized with a footprint of 6 F 2 . Because of its gate terminal, neuron firing is selectively inhibited, which can improve the energy efficiency of the neuromorphic system by inducing sparse activity. Furthermore, the spiking property of the neuron can be controlled by the gate, which can provide additional room to enhance the classification accuracy.
A single transistor neuron (1T‐neuron) is demonstrated by using a vertically protruded nanowire from an 8 in. silicon (Si) wafer. The 1T‐neuron adopts a gate‐all‐around structure to completely ...surround the Si nanowire (Si‐NW) to make a floating body and allow aggressive downscaling. The Si‐NW is composed of an n+ drain at the top, n+ source at the bottom, and p‐type floating body at the middle, which are self‐aligned vertically. Thus, it occupies a small footprint area. The gate controls an excitatory/inhibitory function. In addition, myelination of a biological neuron that changes membrane capacitance is mimicked by an inherently asymmetric source/drain structure. Two spiking frequencies at the same input current are controlled by whether the neuron is myelinated or unmyelinated. Using the vertical 1T‐neuron, pattern recognition is demonstrated with both measurements and semiempirical circuit simulations. Furthermore, handwritten numbers in the MNIST database are recognized with accuracy of 93% by software‐based simulations. Applicability of the vertical 1T‐neuron to various neural networks is verified, including a single‐layer perceptron, multilayer perceptron, and spiking neural network.
A vertical silicon nanowire based single transistor neuron is demonstrated for a neuromorphic system. It can greatly reduce the hardware cost of a neuromorphic system with 4F2 footprint while having important neuronal functions such as leaky integrate‐and‐fire, excitatory/inhibitory, and myelination functions by inspiration of a biological neuron. Moreover, pattern recognition in a system level is demonstrated for various neural networks.
A capacitive synaptic transistor (synaptor) compatible with the fabrication process of conventional Flash memory is proposed for compute-in-memory (CIM) array cells to support energy-efficient ...inference operations. This synaptor demonstrates the highly reliable endurance characteristic of program/erase (P/E) due to overturned charge injection occurring between a control gate (CG) and a floating gate (FG) rather than between the FG and a channel. On- and off- state capacitances (<inline-formula> <tex-math notation="LaTeX">{C}_{\text {on}} </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">{C}_{\text {off}}{)} </tex-math></inline-formula> are determined by the area ratio of CG and FG. After optimizing the pulse conditions, we achieved the P/E endurance of at least 107 cycles and retention time of 104 sec.
A neuromorphic module of an electronic nose (E‐nose) is demonstrated by hybridizing a chemoresistive gas sensor made of a semiconductor metal oxide (SMO) and a single transistor neuron (1T‐neuron) ...made of a metal‐oxide‐semiconductor field‐effect transistor (MOSFET). By mimicking a biological olfactory neuron, it simultaneously detects a gas and encoded spike signals for in‐sensor neuromorphic functioning. It identifies an odor source by analyzing the complicated mixed signals using a spiking neural network (SNN). The proposed E‐nose does not require conversion circuits, which are essential for processing the sensory signals between the sensor array and processors in the conventional bulky E‐nose. In addition, they do not have to include a central processing unit (CPU) and memory, which are required for von Neumann computing. The spike transmission of the biological olfactory system, which is known to be the main factor for reducing power consumption, is realized with the SNN for power savings compared to the conventional E‐nose with a deep neural network (DNN). Therefore, the proposed neuromorphic E‐nose is promising for application to Internet of Things (IoT), which demands a highly scalable and energy‐efficient system. As a practical example, it is employed as an electronic sommelier by classifying different types of wines.
A neuromorphic module of an electronic nose (E‐nose) is demonstrated by hybridizing a semiconductor metal oxide (SMO) and a single transistor neuron (1T‐neuron). By mimicking a biological olfactory neuron, it can perform gas detection and spike encoding simultaneously for in‐sensor neuromorphic functioning. It is helpful to realize a highly scalable and energy‐efficient E‐nose for mobile gas sensors and IoT applications.
A mnemonic-opto-synaptic transistor (MOST) that has triple functions is demonstrated for an in-sensor vision system. It memorizes a photoresponsivity that corresponds to a synaptic weight as a memory ...cell, senses light as a photodetector, and performs weight updates as a synapse for machine vision with an artificial neural network (ANN). Herein the memory function added to a previous photodetecting device combined with a photodetector and a synapse provides a technical breakthrough for realizing in-sensor processing that is able to perform image sensing and signal processing in a sensor. A charge trap layer (CTL) was intercalated to gate dielectrics of a vertical pillar-shaped transistor for the memory function. Weight memorized in the CTL makes photoresponsivity tunable for real-time multiplication of the image with a memorized photoresponsivity matrix. Therefore, these multi-faceted features can allow in-sensor processing without external memory for the in-sensor vision system. In particular, the in-sensor vision system can enhance speed and energy efficiency compared to a conventional vision system due to the simultaneous preprocessing of massive data at sensor nodes prior to ANN nodes. Recognition of a simple pattern was demonstrated with full sets of the fabricated MOSTs. Furthermore, recognition of complex hand-written digits in the MNIST database was also demonstrated with software simulations.
Low-temperature deuterium annealing (LTDA) was applied to a silicon-on-insulator (SOI) n-channel FinFET to improve device performance and reliability. LTDA at 300 °C, which is roughly 100 °C lower ...than a conventional forming gas annealing (FGA) process with hydrogen, is attractive to reduce the thermal budget. To confirm improved performance, the ON-state current (<inline-formula> <tex-math notation="LaTeX">{I}_{\text {on}}{)} </tex-math></inline-formula>, OFF-state current (<inline-formula> <tex-math notation="LaTeX">{I}_{\text {off}}{)} </tex-math></inline-formula>, subthreshold swing (SS), trans-conductance (<inline-formula> <tex-math notation="LaTeX">{g}_{m}{)} </tex-math></inline-formula>, and gate leakage current (<inline-formula> <tex-math notation="LaTeX">{I}_{\text {G}}{)} </tex-math></inline-formula> were evaluated. Thereafter, the parasitic sheet resistance (<inline-formula> <tex-math notation="LaTeX">{R}_{\text {poly,sheet}} </tex-math></inline-formula>) of gate was characterized and compared between before and after LTDA. The decreased <inline-formula> <tex-math notation="LaTeX">{R}_{\text {poly,sheet}} </tex-math></inline-formula> induced by LTDA is attractive for reducing RC delay. In a reliability point of view, damaged device characteristics by intentional hot-carrier injection (HCI) were recovered by LTDA. In addition to electrical analyses of LTDA effects, deuterium to form the Si-D bonds at the Si channel interface was physically mapped along the perpendicular direction to a FinFET by using time-of-flight secondary-ion mass spectrometry (ToF-SIMS).
Leaky characteristic in a leaky integrate-and-fire (LIF) neuron is important to prevent a permanent effect on a single input stimulus in an artificial neuromorphic system as well as a biological ...nerve. In a proposed single-transistor-based LIF neuron (1T-neuron), band-to-band tunneling (BTBT) dominates the leaky characteristic. Three methods to control the leaky characteristic of a 1T-neuron are demonstrated in this work: controlling the relative location of the drain junction edge to a gate, tuning the gate voltage (<inline-formula> <tex-math notation="LaTeX">{V}_{G} </tex-math></inline-formula>), and modulating body doping concentration (<inline-formula> <tex-math notation="LaTeX">{N}_{sub} </tex-math></inline-formula>). The 1T-neuron becomes leakier with a more overlapped drain junction with the gate, decreased <inline-formula> <tex-math notation="LaTeX">{V}_{G} </tex-math></inline-formula>, and increased <inline-formula> <tex-math notation="LaTeX">{N}_{sub} </tex-math></inline-formula> by accelerating the BTBT.
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