Charge sharing between adjacent devices can lead to increased Single Event Upset (SEU) vulnerability. Key parameters affecting charge sharing are examined, and relative collected charge at the hit ...node and adjacent nodes are quantified. Results show that for a twin-well CMOS process, PMOS charge sharing can be effectively mitigated with the use of contacted guard-ring, whereas a combination of contacted guard-ring, nodal separation, and interdigitation is required to mitigate the NMOS charge sharing effect for the technology studied
This Letter presents a millimetre-wave CMOS oscillator, which achieves 4.9 dBm output power with 16% peak power efficiency. A phase noise of ${-98}\,{\rm dBc/Hz}$−98dBc/Hz at 1 MHz offset frequency ...and 26.7% tuning range around 57.5 GHz centre frequency were verified experimentally. To the best knowledge of the authors, the output power, efficiency, and phase noise performance are the best among fundamental CMOS oscillators in the frequency range of interest, while the tuning range is the third highest result reported to date. The circuit occupies a silicon area of ${\sim }{9000}\,{\rm \mu} {\rm m}^2$∼9000μm2 without the matching inductors on a 22 nm fully depleted silicon on insulator (FD-SOI) CMOS technology.
This letter presents a novel technology for the integration of gallium nitride (GaN) power devices with silicon control circuits. It comprises stacked GaN power transistors and ...bipolar-CMOS-double-diffused metal-oxide-semiconductor (DMOS) (BCD) circuits. It leverages on both advantages of the high-voltage low-loss GaN devices and the high-integration BCD circuits. Using conventional manufacturing, packaging, and assembly techniques and equipment, the proposed technology is technology transferrable and applicable for commercial power electronic applications. To validate the concept, a 3.3-70 V dc-dc boost converter is designed, implemented, and verified experimentally. It features a conversion efficiency of 70.3%, output power of 1.68 W, and compact size of <inline-formula><tex-math notation="LaTeX">{\text{0.32}}\times {\text{0.18}}\,{\text{cm}}^{2}</tex-math></inline-formula>.
We present a high-performance back-illuminated three-dimensional stacked single-photon avalanche diode (SPAD), which is implemented in 45-nm CMOS technology for the first time. The SPAD is based on a ...P + /Deep N-well junction with a circular shape, for which N-well is intentionally excluded to achieve a wide depletion region, thus enabling lower tunneling noise and better timing jitter as well as a higher photon detection efficiency and a wider spectrum. In order to prevent premature edge breakdown, a P-type guard ring is formed at the edge of the junction, and it is optimized to achieve a wider photon-sensitive area. In addition, metal-1 is used as a light reflector to improve the detection efficiency further in backside illumination. With the optimized 3-D stacked 45-nm CMOS technology for back-illuminated image sensors, the proposed SPAD achieves a dark count rate of 55.4 cps/μm 2 and a photon detection probability of 31.8% at 600 nm and over 5% in the 420-920 nm wavelength range. The jitter is 107.7 ps full width at half-maximum with negligible exponential diffusion tail at 2.5 V excess bias voltage at room temperature. To the best of our knowledge, these are the best results ever reported for any back-illuminated 3-D stacked SPAD technologies.
Power and RF electronics applications have spurred massive investment into a range of wide and ultrawide bandgap semiconductor devices which can switch large currents and voltages rapidly with low ...losses. However, the end systems using these devices are often limited by the parasitics of integrating and driving these chips from the silicon complementary metal-oxide-semiconductor-based design (CMOS) circuitry necessary for complex control logic. For that reason, implementation of CMOS logic directly in the wide bandgap platform has become a way for each maturing material to compete. This review examines potential CMOS monolithic and hybrid approaches in a variety of wide bandgap materials.
This Letter presents for the first time radio frequency (RF) reliability studies of fully integrated CMOS RF integrated circuits (RFICs) for next generation wireless communication applications ...involving conformal bodies where wireless communication RFICs will be embedded on ultra-thin flexible packages. As a test case, RF characteristics of a CMOS voltage-controlled oscillator (VCO) chip with multiple die-substrate thicknesses were measured and results are analysed. The CMOS VCO chip under study was designed and fabricated using 180 nm RF-CMOS process. Reliability of performances of the VCO chips are characterised and results are compared before and after die thinning from 250 to 50, 35, and 25 μm, respectively. Critical RF performance parameters such as frequency of oscillation, output power, and phase noise are considered for analysis, respectively. All the dies are placed face-up for probing on the top of a metal chuck with ground connection inside the micro-chamber of a probe station. While the deviations of frequency and output power are within ±1% and ±1 dB, respectively, due to the die thinning affect, the phase noise deteriorations are observed significant. It confirms the well-known fact of phase noise sensitiveness to the substrate thickness due to the leakage and SOI CMOS is discussed widely to minimise these parasitic effects.
A Hall magnetic sensor working in the current domain and its electronic interface are presented. The paper describes the physical sensor design and implementation in a standard CMOS technology, the ...transistor level design of its high sensitive front-end together with the sensor experimental characterization. The current-mode Hall sensor and the analog readout circuit have been fabricated using a 0.18- μm CMOS technology. The sensor uses the current spinning technique to compensate for the offset and provides a differential current as an output signal. The measured sensor power consumption and residual offset are 120 μW and 50 μT, respectively.
A new silicon realization of an ultra-low-voltage and ultra-low-power differential-difference amplifier (DDA) is presented in this paper. The circuit combines the idea of non-tailed bulk-driven ...differential pairs with a partial positive feedback used for voltage gain boosting. The DDA operates from VDD ranging from 0.3 to 0.5 V. For a 0.3-V version, the circuit provides measured DC voltage gain larger than 60 dB, the GBW product of 1.85 kHz, PSRR of 57 dB and the average slew-rate of 1.55 V/ms at 20 pF load capacitance, while consuming only 22 nW of power. An instrumentation amplifier based on the proposed DDA showed the THD of 0.5 % for Vin = 50 mVpp, and the 3-dB bandwidth of 750 Hz with the voltage gain of 2 V/V. The circuit has been fabricated in a standard n-well 0.18 μm CMOS process from TSMC. Chip test results agree with simulations. A special design procedure has also been developed that allows the circuit to be optimized under such extreme supply conditions.
Abstract
A three‐stage rail‐to‐rail bulk‐driven class AB OTA that operates with ±0.15 V supplies and a power dissipation of 90 nW is introduced. The first two stages use resistive local common mode ...feedback. The OTA uses simple phase lead compensation. It has a 36 MHz.pF/μW small signal figure of merit and a 55(V/μs) pF/μW large signal figure of merit.
We report on the design and characterization of a multipurpose 64 × 32 CMOS single-photon avalanche diode (SPAD) array. The chip is fabricated in a high-voltage 0.35-μm CMOS technology and consists ...of 2048 pixels, each combining a very low noise (100 cps at 5-V excess bias) 30-μm SPAD, a prompt avalanche sensing circuit, and digital processing electronics. The array not only delivers two-dimensional intensity information through photon counting in either free-running (down to 10-μs integration time) or time-gated mode, but can also perform smart light demodulation with in-pixel background suppression. The latter feature enables phase-resolved imaging for extracting either three-dimensional depth-resolved images or decay lifetime maps, by measuring the phase shift between a modulated excitation light and the reflected photons. Pixel-level memories enable fully parallel processing and global-shutter readout, preventing motion artifacts (e.g., skew, wobble, motion blur) and partial exposure effects. The array is able to acquire very fast optical events at high frame-rate (up to 100 000 fps) and at single-photon level. Low-noise SPADs ensure high dynamic range (up to 110 dB at 100 fps) with peak photon detection efficiency of almost 50% at 410 nm. The SPAD imager provides different operating modes, thus, enabling both time-domain applications, like fluorescence lifetime imaging (FLIM) and fluorescence correlation spectroscopy, as well as frequency-domain FLIM and lock-in 3-D ranging for automotive vision and lidar.
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