Approximate computing is widely used as an efficient method in areas such as digital signal processing (DSP) and machine learning which are inherently error tolerant. This technique can increase the ...speed and reduce the energy consumption of the hardware at the expense of lower accuracy. As the performance of the adder used in a digital signal processor has a significant impact on its speed and power dissipation, this paper presents an approximate error-report-propagate adder (ERPA) in which error compensation occurs from the higher-value to the lower-value bits without any delay overhead. Furthermore, in microarchitectural level, a novel design methodology for implementing and synthesizing hardware accelerators is proposed. In this design, the approximate adders compensate for each other's error without any additional cost. Simulation results show that the proposed adders offer 17% reduction in the mean error distance compared to the other state-of-the-art approximate adders. Furthermore, a dense computational DSP task using the proposed approximate adders is presented. Compared to other conventional approximate adders, our approximation methodologies achieve 9.47%, 42%, and 26% improvements in quality, energy and area, respectively.
The use of microelectromechanical systems' sensors is growing steadily since it is the cheapest way to get information about the inertial state of a moving object. However, preprocessing inertial ...data using hybrid reconfigurability is challenging. This article is an analysis of the noise generated by a multisensory data acquisition and preprocessing system that has been implemented to interface inertial sensors (particularly accelerometers and gyroscopes). A multichannel reconfigurable voltage attenuator (MRVA) based on the field-programmable analog array, an alternative to classical voltage dividers, has been created to interface the sensors with the field-programmable gate array. This article describes a hardware accelerator implementation of two calibration/denoising processes based on the moving average filters in order to select the best choice for the preparation of inertial measurement units data, where a precision of 99.72% was reached. The MRVA is interfaced via Xilinx analog-to-digital converter, where an intellectual property has been designed for hardware acceleration using Xilinx system generator.
The European Commission aims to achieve climate-neutral cities by 2050. In such a complex operational framework, it is necessary to provide decision makers with adequate tools to promote energy ...transition and the resilience of cities through integrated actions, which directly involve communities and end users. To face these challenges and according to the objectives of the National Research Programme, it could be useful to implement interoperable urban digital platforms. Therefore, this contribution proposes a methodological point of view aimed at guiding the planning of shared and conscious redevelopment interventions through the implementation of a decision support platform conceived as an enabling environment capable of systematising data, tools and guidelines for the design and management of policies and interventions at the district scale.
In digital communication, a filter is any device that selectively attenuates any unwanted component from a received signal. It essentially changes or reshapes the waveform of a signal in the desired ...manner. In this work, we have designed and studied low pass filter using Rectangular, Bartlett, Hamming, Hanning, Tukey and Kaiser Window algorithms and compared them with each other for further analysis. The parameters we used for designing the filter are sampling frequency, cut off frequency, filter order and a variable parameter, α. MATLAB toolbox for DSP, namely FDA Tool and FV Tool were employed for the realization of the design.
In this paper, a current control scheme, based on proportional-integral regulators using sinusoidal signal integrators (SSIs), is proposed for shunt type power conditioners. The aim is to simplify ...the implementation of SSI-based current harmonic compensation for industrial implementations where strict limitations on the harmonic distortion of the mains' currents are required. To compensate current harmonics, the SSIs are implemented to operate both on positive and negative sequence signals. One regulator, for the fundamental current component, is implemented in the stationary reference frame. The other regulators, for the current harmonics, are all implemented in a synchronous reference frame rotating at the fundamental frequency. This allows the simultaneous compensation of two current harmonics with just one regulator, yielding a significant reduction of the computational effort compared with other current control methods employing sinusoidal signal integrators implemented in stationary reference frame. A simple and robust voltage filter is also proposed by the authors to obtain a smooth and accurate position estimation of the voltage vector at the point of common coupling (PCC) under distorted mains' voltages. The whole control algorithm has been implemented on a 16-b, fixed-point digital signal processor (DSP) platform controlling a 20-kVA power conditioner prototype. The experimental results presented in this paper for inductive and capacitive loads show the validity of the proposed solutions.
A comprehensive 5 MW wind turbine emulator's design and implementation are designed and investigated thoroughly in this paper. A separately excited DC motor set under the control of a ...current-controlled drive forms the basis of the suggested emulation. The emulation algorithms that simulate the features of the 5 MW wind turbine are run on a digital signal processor (DSP). These algorithms regulate the DC motor's current, which in turn regulates the torque. The results obtained demonstrate that the system was successful in accurately simulating the transient and steady-state characteristics of the 5 MW wind turbine. The emulator system was initially tested and validated with simulation results using MATLAB/Simulink code attached to both the FAST and TurbSim models. Furthermore, step and stochastic wind profiles were used to experimentally verify and test it. Nearly all of the power that is available in the wind turbine system is successfully obtained using the maximum power point tracking technique, which is used to find the best operating point. The created wind turbine emulator can be used to precisely assess energy harvesting by examining various mechanical and electrical properties of the Permanent Magnet Synchronous Generator (PMSG) vastly used in ultra-large wind turbine nacelles.
This paper presents an improved current control strategy for a three-phase grid-connected inverter under distorted grid conditions. The main challenge associated with the grid-connected inverter in ...distributed generation (DG) systems is to maintain the harmonic contents in output current below the specified values even when the grid is subject to uncertain disturbances such as harmonic distortion. To overcome such a challenge, an improved current control scheme is proposed for a grid-connected inverter, in which the fundamental and harmonic currents are independently controlled by a proportional-integral (PI) decoupling controller and a predictive basis controller, respectively. The controller design approach is based on the model decomposition method, where the measured inverter currents and grid voltages are divided into the fundamental and harmonic components by means of moving average filters (MAFs). Moreover, to detect the angular displacement and angular frequency with better accuracy, even in the presence of the grid disturbance, the MAF is also introduced to implement an enhanced phase-lock loop (PLL) structure. Theoretical analyses as well as comparative simulation results demonstrate that the proposed control scheme can effectively compensate the uncertainties caused by the grid voltages with fast transient response. To validate the feasibility of the proposed scheme, the whole control algorithms are implemented on 2 kVA three-phase grid-connected inverter system using 32-bit floating-point DSP TMS320F28335. As a result, the proposed scheme is an attractive way to control a grid-connected inverter under adverse grid conditions.
The embedded visual tracking system has higher requirements for real-time performance and system resources, and this is a challenge for visual tracking systems with available hardware resources. The ...major focus of this study is evaluating the results of hardware optimization methods. These optimization techniques provide efficient utilization based on limited hardware resources. This paper also uses a pragmatic approach to investigate the real-time performance effect by implementing and optimizing a kernel correlation filter (KCF) tracking algorithm based on a vision digital signal processor (vision DSP). We examine and analyze the impact factors of the tracking system, which include DP (data parallelism), IP (instruction parallelism), and the characteristics of parallel processing of the DSP core and iDMA (integrated direct memory access). Moreover, we utilize a time-sharing strategy to increase the system runtime speed. These research results are also applicable to other machine vision algorithms. In addition, we introduced a scale filter to overcome the disadvantages of KCF for scale transformation. The experimental results demonstrate that the use of system resources and real-time tracking speed also satisfies the expected requirements, and the tracking algorithm with a scale filter can realize almost the same accuracy as the DSST (discriminative scale space tracking) algorithm under a vision DSP environment.
•Design a fast-parallel low-level kernel of the Complex Matrix Multiplication algorithm based on modulo-scheduling, software pipelining and loop unrolling techniques.•Suggest a novel approach of ...implementing the Complex Matrix Multiplication algorithm based on the fast-parallel kernel and the miss-pipelining technique.•Introduce an ultra-optimized parallel implementation approach based on the fast-parallel kernel and the internal direct memory access data transfer technique.•Accelerate the beamforming and Doppler Filter Bank algorithms to meet tight real-time constraints of radar applications.
The Complex Matrix Multiplication (CMM) algorithm is known to require a high computing performance and presenting exceptional challenges in real-life applications. Recent advances in Very Long Instruction Word (VLIW) based Digital Signal Processors (DSP) demonstrated high computing capabilities with a very low power consumption. In this work, we propose three ultra-fast, parallel and efficient VLIW implementation approaches of the CMM algorithm which could be used to meet tighter real-time constraints of several signal and image processing applications like radars. A novel parallel kernel, task mapping strategy and low-level optimization techniques are suggested, to fit a set of modern VLIW architectures. Additionally, an original memory access management technique was adopted to accelerate the algorithm by avoiding cache misses and bank conflicts. The experimental results showed the effectiveness of the proposed approaches where a peak performance of 15.89 GFLOPS was achieved on one C66x DSP core with a core utilization of 99% and a speedup of about 1.61, 3 and 10 compared to the state-of-the-art, the most optimized vendor and the conventional approaches, respectively.
Display omitted
PDF
