A crosstalk compensation (XTC) receiver is proposed for a single-ended four-level pulse amplitude modulation (PAM-4) signaling DRAM interface. The receiver compensates for the crosstalk from two ...adjacent pin signals by using an RC circuit per pin. The transmitter of the test chip consists of a voltage-mode PAM-4 driver and a three-tap feed-forward equalizer. The XTC circuit at the test chip receiver consists of six blocks of a current-integrating differential amplifier per pin. The current integrating differential amplifier includes three differential pairs, one for its own pin data and the other two for adjacent pin data. The test chip, fabricated on a 28-nm CMOS low-power process, worked successfully at a data rate of 24 Gb/s per pin with four parallel 5-cm long microstrip lines on an FR-4 printed circuit board. The width was 14-mil and the center-to-center spacing was 35-mil. Compared to the previous crosstalk compensation scheme that uses three or more multi-pins, each with one RC circuit and two CR circuits per pin, the transmission coefficient at the receiver input pin was enhanced by 1.31 dB from -1.89 dB to -0.58 dB at the Nyquist frequency of 6 GHz. The XTC circuit opened the closed eyes of both the second and the third pin data among the four data pins of the test chip to 0.12 UI at 24 Gb/s per pin with PAM-4 signaling and bit error rate of 10<inline-formula> <tex-math notation="LaTeX">^{-12}</tex-math> </inline-formula>. The energy efficiency of the receiver test chip was 1.28 pJ/bit at the 1.1 V supply.
Many graph mining algorithms process large graphs with several passes and suffers from huge I/O cost. GraphIdx, an open-source C library, facilitates a memory-efficient indexing of large graphs to ...reduce that I/O cost. GraphIdx indexes a block of graph data for a set of nodes based on the empirical evaluation of edges. Due to the indexed graph, graph mining algorithms can access and process only the related nodes and their edges instead of scanning entire graph. As a result, the number of I/Os is significantly reduced. Moreover, GraphIdx accredited algorithms can process graphs in parallel due to the indexed data.
•An algorithm to construct an index table for accessing graph data selectively.•Avoid full scan to read a part of the graph and reduce the I/O cost significantly.•Parallelize graph mining algorithms by processing indexed data simultaneously.•An open-source C library to construct and exploit indices for efficient graph mining.
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This study sought to quantitate total blood volume (TBV) in patients hospitalized for decompensated chronic heart failure (DCHF) and to determine the extent of volume overload, and the magnitude and ...distribution of blood volume and body water changes following diuretic therapy.
The accurate assessment and management of volume overload in patients with DCHF remains problematic.
TBV was measured by a radiolabeled-albumin dilution technique with intravascular volume, pre-to-post-diuretic therapy, evaluated at hospital admission and at discharge. Change in body weight in relation to quantitated TBV was used to determine interstitial volume contribution to total fluid loss.
Twenty-six patients were prospectively evaluated. Two patients had normal TBV at admission. Twenty-four patients were hypervolemic with TBV (7.4 ± 1.6 liters) increased by +39 ± 22% (range, +9.5% to +107%) above the expected normal volume. With diuresis, TBV decreased marginally (+30 ± 16%). Body weight declined by 6.9 ± 5.2 kg, and fluid intake/fluid output was a net negative 8.4 ± 5.2 liters. Interstitial compartment fluid loss was calculated at 6.2 ± 4.0 liters, accounting for 85 ± 15% of the total fluid reduction.
TBV analysis demonstrated a wide range in the extent of intravascular overload. Dismissal measurements revealed marginally reduced intravascular volume post-diuretic therapy despite large reductions in body weight. Mobilization of interstitial fluid to the intravascular compartment with diuresis accounted for this disparity. Intravascular volume, however, remained increased at dismissal. The extent, composition, and distribution of volume overload are highly variable in DCHF, and this variability needs to be taken into account in the approach to individualized therapy. TBV quantitation, particularly serial measurements, can facilitate informed volume management with respect to a goal of treating to euvolemia.
High‐speed I/O channels require adaptive techniques to optimize the settings for filter tap weights at decision feedback equalization (DFE) read channels to compensate for channel inter‐symbol ...interference (ISI) and crosstalk from multiple adjacent channels. Both ISI and crosstalk tend to vary with channel length, process, and temperature variations. Individually optimizing parameters such as those just mentioned leads to suboptimal solutions. We propose a joint optimization technique for crosstalk cancellation (XTC) at DFE to compensate for both ISI and XTC in high‐speed I/O channels. The technique is used to compensate for between 15.7 dB and 19.7 dB of channel loss combined with a variety of crosstalk strengths from 60 mVp‐p to 180 mVp‐p adaptively, where the transmit non‐return‐to‐zero signal amplitude is a constant 500 mVp‐p.
Abstract
Data updates have become an important issue in erasure-coded in-memory stores owing to the two-fold reasons: (i) a handful of data-intensive in-memory stores adopt erasure coding for ‘hot’ ...data and (ii) small writes in update-intensive in-memory workloads cause expensive updating overheads. After delving into prior updating schemes in erasure-coded storage clusters, we investigate the applicability of these schemes to erasure-coded in-memory stores. We propose a grouped-updating mechanism—GU—to handle small writes in in-memory stores. With GU in place, requests in an updating window are categorized into several updating groups, where multiple small updates in an updating group can be concurrently executed. Two GU updating procedures—GU-stripe and GU-node—are developed to schedule updates according to a stripe and a node holding an updated data block, respectively. Furthermore, we develop two hybrid-updating schemes—Hybrid−UGU-stripe and Hybrid−UGU-node—to process common writes (i.e. small and large writes) initiated by the GU-stripe- and GU-node-based updating schemes, respectively. Replaying an update-heavy workload generated by YCSB benchmark, we extensively evaluate the four non-GU-based updating schemes, five GU-stripe-based updating schemes, and five GU-node-based updating schemes. Our experiments demonstrate that the GU mechanism boosts updating performance of small writes for RS-coded in-memory stores in terms of updating time and updating traffic. In particular, for a (8, 6) RS-coded in-memory store, the GU-stripe- and GU-node-based updating schemes shortens the updating time of the non-GU-based counterparts by a factor of at least 2.08 and 2.66, respectively. Compared to a single GU-based updating scheme, a GU-based hybrid updating scheme achieves an optimal updating-time and updating-traffic performance.
A crosstalk cancellation and signal reutilization (XTCR) analog front-end implemented with infinite impulse response (IIR) networks dramatically improves signal integrity across multiple ...closely-spaced single-ended PCB traces. The XTCR technique has been designed to address multiple high-speed I/Os from the ground up. To verify this technique a 4 channel prototype was implemented in 65 nm CMOS. This 4 channel prototype design handles crosstalk cancellation for single-ended I/Os operating at 12 Gb/s. At this speed, the prototype XTCR design improves the measured average horizontal and vertical-eye openings by 37.5% and 26.4% at 10 -8 BER, while consuming only 0.96 pJ/b/lane.
In this paper, an efficient page rank (PR) exact algorithm is proposed, which can improve the computation efficiency without sacrificing results accuracy. The existing exact algorithms are generally ...based on the original power method (PM). In order to reduce the number of I/Os required to improve efficiency, they partition the big graph into multiple smaller ones that can be totally fitted in memory. The algorithmproposed in this paper can further reduce the required number of I/Os. Instead of partitioning the graph into the general subgraphs, our algorithm partitions graph into a special kind of subgraphs: SCCs (strongly connected components), the nodes in which are reachable to each other. By exploiting the property of SCC, some theories are proposed, based on which the computation iterations can be constrained on these SCC subgraphs. Our algorithm can reduce lots of I/Os and save a large amount of computations, as well as keeping the results accuracy. In a word, our algorithm is more efficient among the existing exact algorithms. The experiments demonstrate that the algorithms proposed in this paper can make an obvious efficiency improvement and can attain high accurate results.
A continuous-time multiple-input multiple-output crosstalk cancellation (MIMO-XTC) architecture operating at 2-6 Gb/s has been proposed. The performance of the XTC equalizer has been measured with ...various spacings of FR4 channels and data rates. The crosstalk energy reutilization technique efficiently handles crosstalk and achieves high signal integrity in severe crosstalk environments where crosstalk had completely closed the data eye. Measurement results show improvement in jitter p- p and vertical opening of the eye diagram by 67% UI and 58.2%, respectively, which is the best known improvement to date. The MIMO-XTC portion occupies 0.03 mm 2 and consumes 2.8 mW/Gbps/lane, which is two times lower than previously proposed XTC schemes.
Thermal mechanism cover the mechanics of Hit Sink, Airflow mechanics, and Ambient Temperature Mechanism to reduce junction temperature in design of Finite Duration Impulse Response (FIR) Filter. In ...this work, we are implementing FIR Filter on 28nm FPGA. After implementation of FIR Filter, we analyze the effect of in-built mechanism of Air Flow Controller and their produced Airflow on the junction temperature of FPGA. The mechanism of Ambient Temperature controller also play significant role in leakage power dissipation as well as junction temperature of FPGA. Finally, the mechanical structure of Hit Sink is considered for control of junction temperature of FPGA. There is 73.38% reduction in Leakage Power on 55 C ambient temperature when we increase airflow from 250 LFM to 500 LFM. Along with 500 LFM airflow, if we provide high profile hit sink then there is 78.31% reduction in leakage power. There is 37.68% reduction in junction temperature of FPGA when we increase airflow from 250LFM to 500LFM. Along with 500 LFM airflow, if we provide high profile hit sink then there is 41.76 % reduction in junction temperature on 45C ambient temperature. There is no effect of airflow on clock power. Whereas there is significant reduction in Logic Power, Signal Power, DSPs Power and IOs Power with change in Airflow.
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