This study outlines the design, construction and characterization of a tailored low-cost linear birdcage (BC) resonator for magnetic resonance imaging at 7T. Typically, different BC designs found in ...literature are well described in theory but lack crucial information for practical realization. This is challenging, as theoretical and practical aspects often differ greatly from each other, especially in the field of high frequency technology. We propose a simple and open-source 3D printable design which results in a working BC if the instructions in this publication are followed. The aim is to open up the possibility of building a functioning BC with simple means and a budget below 750 €, even for users without a great deal of expertise in MRI coil building. We demonstrate that the BC can achieve a good
B
1
field homogeneity using the double angle method. The proposed design is qualitatively compared to a commercially available resonator. Both perform equally well in terms of SNR and image quality.
Greetings! I am elated to write an article for the IEEE EMC Magazine on the “Student EMC Hardware Design Contest 2022” as part of the 2022 IEEE International Symposium on EMC+SIPI in Spokane, ...Washington (August 1–5, 2022).
Nichtlineare Regelung mit einem Raspberry PI Sven-Olaf Lindert; Höfler, Christian; Schlacher, Kurt
Elektrotechnik und Informationstechnik,
01/2018, Letnik:
135, Številka:
3
Journal Article
Recenzirano
Die kommerziell erhältlichen Automatisierungssysteme sind sehr kostspielig. Hinzu kommen meist Lizenzgebühren für Software zur Simulation und Automatisierung. In diesem Artikel wird die Lösung einer ...anspruchsvollen Automatisierungsaufgabe, die Balancierung eines Balles auf einem rotierenden Rad, durch offene Software und preiswerte Hardware beschrieben. Zum Einsatz kommen der Einplatinencomputer Raspberry PI, das offene Hardware-Automationssystem BIOE und offene Software.
Heracles: Improving resource efficiency at scale Lo, David; Liqun Cheng; Govindaraju, Rama ...
2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA),
06/2015
Conference Proceeding
Odprti dostop
User-facing, latency-sensitive services, such as websearch, underutilize their computing resources during daily periods of low traffic. Reusing those resources for other tasks is rarely done in ...production services since the contention for shared resources can cause latency spikes that violate the service-level objectives of latency-sensitive tasks. The resulting under-utilization hurts both the affordability and energy-efficiency of large-scale datacenters. With technology scaling slowing down, it becomes important to address this opportunity. We present Heracles, a feedback-based controller that enables the safe colocation of best-effort tasks alongside a latency-critical service. Heracles dynamically manages multiple hardware and software isolation mechanisms, such as CPU, memory, and network isolation, to ensure that the latency-sensitive job meets latency targets while maximizing the resources given to best-effort tasks. We evaluate Heracles using production latency-critical and batch workloads from Google and demonstrate average server utilizations of 90% without latency violations across all the load and colocation scenarios that we evaluated.
VHDL, the IEEE standard hardware description language for describing digital electronic systems, allows engineers to describe the structure and specify the function of a digital system as well as ...simulate and test it before manufacturing. In addition, designers use VHDL to synthesize a more detailed structure of the design, freeing them to concentrate on more strategic design decisions and reduce time to market. Adopted by designers around the world, the VHDL family-of-standards have recently been revised to address a range of issues, including portability across synthesis tools. This best-selling comprehensive tutorial for the language and authoritative reference on its use in hardware design at all levels, from system to gates, has been revised to reflect the new IEEE standard, VHDL-2001. The author presents the entire description language and builds a modeling methodology based on successful software engineering techniques. This second edition updates the first, retaining the author’s unique ability to teach this complex subject to a broad audience of students and practicing professionals.
Convolutional neural network (CNN) has become a successful algorithm in the region of artificial intelligence and a strong candidate for many computer vision algorithms. But the computation ...complexity of CNN is much higher than traditional algorithms. With the help of GPU acceleration, CNN-based applications are widely deployed in servers. However, for embedded platforms, CNN-based solutions are still too complex to be applied. Various dedicated hardware designs on field-programmable gate arrays (FPGAs) have been carried out to accelerate CNNs, while few of them explore the whole design flow for both fast deployment and high power efficiency. In this paper, we investigate state-of-the-art CNN models and CNN-based applications. Requirements on memory, computation and the flexibility of the system are summarized for mapping CNN on embedded FPGAs. Based on these requirements, we propose Angel-Eye, a programmable and flexible CNN accelerator architecture, together with data quantization strategy and compilation tool. Data quantization strategy helps reduce the bit-width down to 8-bit with negligible accuracy loss. The compilation tool maps a certain CNN model efficiently onto hardware. Evaluated on Zynq XC7Z045 platform, Angel-Eye is 6× faster and 5× better in power efficiency than peer FPGA implementation on the same platform. Applications of VGG network, pedestrian detection and face alignment are used to evaluate our design on Zynq XC7Z020. NIVIDA TK1 and TX1 platforms are used for comparison. Angel-Eye achieves similar performance and delivers up to 16× better energy efficiency.
The hardware Trojan (HT) has become a major threat for the integrated circuit (IC) industry and supply chain, and has motivated numerous developments of Trojan detection schemes. Although the ...side-channel method is the most promising one, nearly all of the side-channel methods require fabricated golden chips, which are very difficult to obtain in reality. In this paper, we propose a novel strategy for HT detection using electromagnetic side-channel-based spectrum modeling and analyzing. We utilize the design data at early stage of the IC lifecycle, and the generated spectrum can serve as the golden reference, and thus we do not need the fabricated golden chips anymore. Another very important feature is that our method is immune to the process variation theoretically. Experimental results on selected Advanced Encryption Standard benchmark circuits on FPGA show that our proposed method can effectively detect Trojans even with very small traces.
The advent of quantum computing threatens to break many classical cryptographic schemes, leading to innovations in public key cryptography that focus on post-quantum cryptography primitives and ...protocols resistant to quantum computing threats. Lattice-based cryptography is a promising post-quantum cryptography family, both in terms of foundational properties as well as in its application to both traditional and emerging security problems such as encryption, digital signature, key exchange, and homomorphic encryption. While such techniques provide guarantees, in theory, their realization on contemporary computing platforms requires careful design choices and tradeoffs to manage both the diversity of computing platforms (e.g., high-performance to resource constrained), as well as the agility for deployment in the face of emerging and changing standards. In this work, we survey trends in lattice-based cryptographic schemes, some recent fundamental proposals for the use of lattices in computer security, challenges for their implementation in software and hardware, and emerging needs for their adoption. The survey means to be informative about the math to allow the reader to focus on the mechanics of the computation ultimately needed for mapping schemes on existing hardware or synthesizing part or all of a scheme on special-purpose har dware.
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