Amorphous InGaZnO (a-IGZO) is a candidate material for thin-film transistors (TFTs) owing to its large electron mobility and good uniformity over large area. a-IGZO TFTs drain current models are ...essential for further pushing both a-IGZO TFTs technology and circuit design. In this paper, we propose a simple physical-based and analytical model of the drain current of a-IGZO TFTs. The model is valid in both non degenerate and degenerate conduction and it accounts for deep interface states, tail localized states, and free delocalized band states. The model is validated with the measurements of both coplanar and staggered a-IGZO TFTs. It provides key physical and material parameters of the transistor and, owing to its class C ∞ formulation, it can be straightforwardly implemented in circuit simulators.
Performance and reliability comparison of oxide-based thin-film transistors fabricated at a maximum process temperature of 115 °C is presented. A fully patterned and passivated process was ...successfully evaluated and implemented using polycrystalline ZnO and amorphous indium-gallium-zinc-oxide (IGZO) as an active layer in glass substrates. Saturation mobilities of 14.2 and 9.0 cm<inline-formula> <tex-math notation="LaTeX">^{{2}}\cdot \text{V}^{-{1}}\cdot \text{s}^{-{1}} </tex-math></inline-formula> were obtained for ZnO and IGZO, respectively, with threshold voltages of 2.2 and 2.0 V, an ON/ OFF ratio <inline-formula> <tex-math notation="LaTeX">> {1} \times 10^{{8}} </tex-math></inline-formula>, and an <inline-formula> <tex-math notation="LaTeX">{I}_{{\text {off}}}< {1} \times 10^{-{12}} </tex-math></inline-formula> A. The small mobility change in IGZO with gate voltage is due to its amorphous character. Longer variation is observed in polycrystalline ZnO due to its grain boundaries. Reliability studies show a threshold voltage shifting of 0.4 and 1.8 V for ZnO and IGZO devices, testing after 1200-s stress. Devices were successfully implemented in ZnO- and IGZO-based inverters using saturation and zero-drive structures, showing a maximum dc gain of 2.4- and 25-V/V, respectively.
Carbon nanotube (CNT) thin-film transistor (TFT) is a promising candidate for flexible and wearable electronics. However, it usually suffers from low semiconducting tube purity, low device yield, and ...the mismatch between p- and n-type TFTs. Here, we report low-voltage and high-performance digital and analog CNT TFT circuits based on high-yield (19.9%) and ultrahigh purity (99.997%) polymer-sorted semiconducting CNTs. Using high-uniformity deposition and pseudo-CMOS design, we demonstrated CNT TFTs with good uniformity and high performance at low operation voltage of 3 V. We tested forty-four 2-µm channel 5-stage ring oscillators on the same flexible substrate (1,056 TFTs). All worked as expected with gate delays of 42.7 ± 13.1 ns. With these high-performance TFTs, we demonstrated 8-stage shift registers running at 50 kHz and the first tunable-gain amplifier with 1,000 gain at 20 kHz. These results show great potentials of using solution-processed CNT TFTs for large-scale flexible electronics.
This letter investigates degradation after negative bias temperature instability (NBTI) stress applied to LTPS TFTs with different polycrystalline-silicon grain sizes. The initial characteristics of ...the LTPS TFTs are similar regardless of grain size; however, we observed a different degree of degradation after NBTI depending on grain size. In general, after NBTI, both grain boundary traps and interface traps were generated. We found that the degree of NBTI degradation is dominated by the concentration of grain boundary traps, which themselves are a result of the different grain sizes that occur due to excimer laser annealing energy. At initial, dangling bonds in the grain boundaries and at the interface are passivated by hydrogen atoms, hence the initial characteristics are similar. Since the large grain of poly-Si initially generates more dangling bonds in the grain boundaries, after NBTI, hydrogen depassivation generates more grain boundary traps and causes much more serious degradation in device performance.
Active matrix organic-light-emitting-diode (AM OLED) panels, driven by organic thin-film transistors (OTFT), have been successfully fabricated on a flexible plastic substrate. The pixel circuit ...consists of two bottom-contact pentacene OTFTs working as switching and driving transistors. The panel has 16 /spl times/ 16 pixels, each of which have an OLED using a phosphorescent material with an emission efficiency of 30 cd/A. A tantalum oxide (Ta/sub 2/O/sub 5/) film with a dielectric constant of 24, prepared by the anodization of Tantalum (Ta), was used as the gate insulator of the OTFTs. The passivation layer on the OTFTs was formed by a layer of silicon dioxide (SiO/sub 2/) and two layers of polyvinyl alcohol. Using OTFTs with a Ta/sub 2/O/sub 5/ gate insulator, the authors have realized a flexible active matrix OLED panel driven with a low voltage of -12 V.
A solution-processed low operating voltage dual gated metal oxide thin film transistor (TFT) has been fabricated for pressure sensing applications. This device has been fabricated on a p-doped Si (p ...+ -Si) using Li-Alumina (Li-Al 2 O 3 ) as a bottom gate dielectric and SnO 2 thin film as a semiconductor channel. Besides, piezoelectric poly(vinylidene fluoride-co-hexafluoropropylene) (PVDF-HFP) thin film has been utilized as the top gate and dielectric on which external pressure has been applied. During bottom gate biasing, this TFT shows an n-channel behavior within 2 V operating voltage. Under such operation, the obtained value of threshold voltage (V th ), carrier mobility (μ), and On/Off ratio of this device is 0.12 V, 2.60 cm 2 .V -1 .s -1 , and 1.21 × 10 4 , respectively. After applying pressure under accumulation mode operation, drain current (I D ) of the device reduces and the OFF current factor increases. Besides, the V th of the device shifts towards higher positive gate voltage when external pressure has varied from 0.8 mbar to 1.6 bar. The drain current reduction, enhancement of OFF current factor, and V th shifting during the application of pressure of 1.6 bar are 50, 300, and 2000% respectively w.r.t their normal operation. The variation of all these parameters has two distinct regions with good linearity, one is < 80 mbar and the other is > 80 mbar, which is due to the saturation of orientation of the electric dipole of PVDF-HFP under a certain pressure range (< 80 mbar). Moreover, device response and recovery time are 90 and 5 ms respectively, indicating its prompt response to external pressure.
Degradation and failure behaviors of the flexible low-temperature poly-Si (LTPS) thin film transistors (TFTs) under repetitive stretch stress parallel to channel length (<inline-formula> <tex-math ...notation="LaTeX">{L} </tex-math></inline-formula>) direction are investigated. A geometric effect is observed in degradation of the threshold voltage (<inline-formula> <tex-math notation="LaTeX">\Delta {V}_{\text {TH}} </tex-math></inline-formula>), which depends on the channel width (<inline-formula> <tex-math notation="LaTeX">{W} </tex-math></inline-formula>) and active area (<inline-formula> <tex-math notation="LaTeX">\textit {WL} </tex-math></inline-formula>), while has a weak correlation with <inline-formula> <tex-math notation="LaTeX">{L} </tex-math></inline-formula>. Three failure modes of TFTs are identified from their <inline-formula> <tex-math notation="LaTeX">{I} </tex-math></inline-formula>-<inline-formula> <tex-math notation="LaTeX">{V} </tex-math></inline-formula> characteristics: damage in the gate insulator (GI), channel traps generation, and metal line cracks. Failure statistics show that the GI failure has a low failure rate and follows the exponential distribution, while the other two modes have high failure rates in the early stage of the stretch cycles, and their failure distributions follow the limited failure population (LFP) model.
The effect of light illumination intensity on the stability of In-Zn-Sn-O (IZTO) thin-film transistors (TFTs) array fabricated by solution processed is investigated. Comparison with positive bias ...stress, the light illumination suppresses the <inline-formula> <tex-math notation="LaTeX">{V}_{\text {th}} </tex-math></inline-formula> shift under positive bias illumination stress because of the increase in the free electrons induced by the ionized oxygen vacancies in the IZTO channel layer, but transfer characteristics show two-stage degradation under negative bias illumination stress (NBIS). The hump phenomenon is induced after NBIS, and the light illumination intensity is higher, the hump phenomenon becomes more serious. The hump phenomenon is relevant to ionized oxygen vacancies, which act as shallow donor-like states near the conduction-band minimum in IZTO.
Oxide semiconductors are promising channel materials for hafnia-based ferroelectric transistor memories because they can constrain the formation of an unwanted interfacial layer that can deteriorate ...the stability of the device. A major obstacle is the limited memory window, originating from insufficient polarization switching because <inline-formula> <tex-math notation="LaTeX">{n} </tex-math></inline-formula>-type oxide semiconductors cannot provide sufficient hole carriers to realize ferroelectric polarization switching. To solve this issue, a novel design strategy is proposed to achieve increased polarization switching while maintaining the stability of oxide semiconductor-based ferroelectric thin-film transistors (FeTFTs). By inserting an additional <inline-formula> <tex-math notation="LaTeX">{p} </tex-math></inline-formula>-type CuOx layer between the <inline-formula> <tex-math notation="LaTeX">{n} </tex-math></inline-formula>-type oxide semiconductor InZnOx and ferroelectric HfZrOx, increased polarization switching is achieved owing to the high electron and hole densities in the InZnOx and CuOx layers, respectively. Thus, a memory window of 4 V is achieved, which cannot be obtained using a single oxide-semiconductor channel. We also demonstrate that the proposed method is viable for three-dimensional ferroelectric NAND (3D FeNAND) devices. In 3D FeNAND, replacing the dielectric filler with <inline-formula> <tex-math notation="LaTeX">{p} </tex-math></inline-formula>-type CuOx maximizes polarization switching and enlarges the memory window. The results demonstrate a novel structure and fabrication method for high-performance FeTFTs for advanced 3D non-volatile memory applications.
High-performance ZnO thin-film transistors (TFTs) have been successfully fabricated by atomic layer deposition (ALD) with a maximum temperature of 200 °C. The impacts of deposition and annealing ...temperature on the characteristics of devices were discussed. ZnO thin films show a (002) preferred orientation at the high growth temperature. The carrier concentrations of ZnO TFTs can be optimized by appropriate growth temperature and annealing treatments. Subthreshold swing (SS) and hysteresis windows of TFTs are improved after annealing in dry O 2 due to the reduction in traps at ZnO/SiO 2 interface or/and within the ZnO channel. The ZnO TFT deposited at 150 °C with 200 °C annealing in oxygen demonstrates excellent electrical characteristics with high saturation mobility μsat of 7.8 cm 2 V -1 s -1 , small SS of 127 mV/decade, high I ON /I OFF of 2.8 x 10 9 , and good contact between source/drain electrodes. The high-performance ZnO TFTs with low processing temperatures have great potential in application for flexible electronics.
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