The growth, morphological, and electrical properties of thin-film Ge grown by molecular beam epitaxy on Si using a two-step growth process were investigated. High-resolution x-ray diffraction analysis demonstrated ∼0.10% tensile-strained Ge epilayer, owing to the thermal expansion coefficient mismatch between Ge and Si, and negligible epilayer lattice tilt. Micro-Raman spectroscopic analysis corroborated the strain-state of the Ge thin-film. Cross-sectional transmission electron microscopy revealed the formation of 90    ° Lomer dislocation network at Ge/Si heterointerface, suggesting the rapid and complete relaxation of Ge epilayer during growth. Atomic force micrographs exhibited smooth surface morphology with surface roughness < 2 nm. Temperature dependent Hall mobility measurements and the modelling thereof indicated that ionized impurity scattering limited carrier mobility in Ge layer. Capacitance- and conductance-voltage measurements were performed to determine the effect of epilayer dislocation density on interfacial defect states (D it ) and their energy distribution. Finally, extracted D it values were benchmarked against published D it data for Ge MOS devices, as a function of threading dislocation density within the Ge layer. The results obtained were comparable with Ge MOS devices integrated on Si via alternative buffer schemes. This comprehensive study of directly-grown epitaxial Ge-on-Si provides a pathway for the development of Ge-based electronic devices on Si.