VHDL, the IEEE standard hardware description language for describing digital electronic systems, allows engineers to describe the structure and specify the function of a digital system as well as simulate and test it before manufacturing. In addition, designers use VHDL to synthesize a more detailed structure of the design, freeing them to concentrate on more strategic design decisions and reduce time to market. Adopted by designers around the world, the VHDL family-of-standards have recently been revised to address a range of issues, including portability across synthesis tools. This best-selling comprehensive tutorial for the language and authoritative reference on its use in hardware design at all levels, from system to gates, has been revised to reflect the new IEEE standard, VHDL-2001. The author presents the entire description language and builds a modeling methodology based on successful software engineering techniques. This second edition updates the first, retaining the author’s unique ability to teach this complex subject to a broad audience of students and practicing professionals.