The impact of high-order integrator dynamics on switched-capacitor sigma-delta modulator (¿¿M) performances is investigated in this paper. An advanced generic integrator-settling model to take into account high-order dynamic effects is presented and validated by means of transistor-level simulations of circuits implemented in a commercial 0.35 ¿m CMOS technology. The model is used through the paper to carry out an exhaustive behavioral analysis for second-order single-bit ¿¿Ms characterized by first-, second-, and third-order integrator dynamics, showing how high-order poles and zeros can affect the ¿¿M characteristics remarkably. The proposed analysis provides useful guidelines to fix a convenient integrator poles/zeros placement in order to achieve an effective ¿¿M design flow.