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Budiman, A.S.; Shin, H.-A.-S.; Kim, B.-J.; Hwang, S.-H.; Son, H.-Y.; Suh, M.-S.; Chung, Q.-H.; Byun, K.-Y.; Tamura, N.; Kunz, M.; Joo, Y.-C.
Microelectronics and reliability, 03/2012, Letnik: 52, Številka: 3Journal Article
Display omitted Through-silicon via (TSV) has been used for 3-dimentional integrated circuits. Mechanical stresses in Cu and Si around the TSV were measured using synchrotron X-ray microdiffraction. The hydrostatic stress in Cu TSV went from high tensile of 234MPa in the as-fabricated state, to −196MPa (compressive) during thermal annealing (in situ measurement), to 167MPa in the post-annealed state. Due to this stress, the keep-away distance in Si was determined to be about 17μm. Our results suggest that Cu stress may lead to reliability as well as integration issues, while Si stress may lead to device performance concerns.
